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8SLVD2104 PDF 데이터시트 : 부품 기능 및 핀배열

부품번호 8SLVD2104
기능 LVDS Output Fanout Buffer
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8SLVD2104 데이터시트, 핀배열, 회로
Dual 1:4, LVDS Output Fanout Buffer
8SLVD2104
DATA SHEET
General Description
The 8SLVD2104 is a high-performance differential dual 1:4 LVDS
fanout buffer. The device is designed for the fanout of high-frequency,
very low additive phase-noise clock and data signals. The
8SLVD2104 is characterized to operate from a 2.5V power supply.
Guaranteed output-to-output and part-to-part skew characteristics
make the 8SLVD2104 ideal for those clock distribution applications
demanding well-defined performance and repeatability. Two
independent buffers with four low skew outputs each are available.
The integrated bias voltage generators enables easy interfacing of
single-ended signals to the device inputs. The device is optimized for
low power consumption and low additive phase noise.
Features
• Two 1:4, low skew, low additive jitter LVDS fanout buffers
• Two differential clock inputs
• Differential pairs can accept the following differential input
levels: LVDS and LVPECL
• Maximum input clock frequency: 2GHz
• Output bank skew: 35ps, (maximum)
• Propagation delay: 300ps, (maximum)
• Low additive RMS phase jitter, 156.25MHz (10kHz - 20MHz):
105fs, (maximum)
• 2.5V supply voltage
• Lead-free (RoHS 6) 28-Lead VFQFN package
• -40°C to 85°C ambient operating temperature
Block Diagram
Pin Assignment
28 27 26 25 24 23 22
GND 1
21 nQA3
QB3 2
20 QA3
nQB3 3
EN 4
8SLVD2104 19 nQA2
18 QA2
PCLKB 5
17 nQA1
nPCLKB 6
16 QA1
VREFB 7
15 VDD
8 9 10 11 12 13 14
28-Lead, 5mm x 5mm VFQFN
8SLVD2104 REVISION 1 08/03/15
1 ©2015 Integrated Device Technology, Inc.




8SLVD2104 pdf, 반도체, 판매, 대치품
8SLVD2104 DATA SHEET
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress
specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Electrical Characteristics
or AC Electrical Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product
reliability.
Item
Supply Voltage, VDD
Inputs, VI
Outputs, IO (LVDS)
Continuous Current
Surge Current
Maximum Junction Temperature, TJ,MAX
Storage Temperature, TSTG
ESD - Human Body Model1
ESD - Charged Device Model1
NOTE 1: According to JEDEC/JESD JS-001-2012/22-C101E.
Rating
4.6V
-0.5V to VDD + 0.5V
10mA
15mA
125C
-65C to 150C
2000V
1500V
DC Electrical Characteristics
Table 4A. Power Supply Characteristics, VDD = 2.5V ± 5%, TA = -40°C to 85°C1
Symbol Parameter
Test Conditions
Minimum
VDD Power Supply Voltage
IDD Power Supply Current
All outputs terminated with 100in
between nQx, Qx; DC to 2GHz
2.375
NOTE 1: Qx, nQx denotes QA[3:0], nQA[3:30], and QB[3:0], nQB[3:0].
Typical
2.5
145
Maximum
2.625
170
Units
V
mA
Table 4B. LVCMOS/LVTTL Input Characteristics, VDD = 2.5V ± 5%, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
VMID
Input Voltage -
Open Pin
EN
Open
VIH Input High Voltage EN
VIL Input Low Voltage EN
IIH Input High Current EN
IIL Input Low Current EN
VDD = VIN = 2.625V
VDD = 2.625V, VIN = 0V
0.7 * VDD
-0.3
-150
Typical
VDD / 2
Maximum
VDD + 0.3
0.2 * VDD
150
Units
V
V
V
µA
µA
DUAL 1:4, LVDS OUTPUT FANOUT BUFFER
4
REVISION 1 08/03/15

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8SLVD2104 전자부품, 판매, 대치품
8SLVD2104 DATA SHEET
Additive Phase Jitter
The spectral purity in a band at a specific offset from the fundamental
compared to the power of the fundamental is called the dBc Phase
Noise. This value is normally expressed using a Phase noise plot
and is most often the specified plot in many applications. Phase noise
is defined as the ratio of the noise power present in a 1Hz band at a
specified offset from the fundamental frequency to the power value of
the fundamental. This ratio is expressed in decibels (dBm) or a ratio
of the power in the 1Hz band to the power in the fundamental. When
the required offset is specified, the phase noise is called a dBc value,
which simply means dBm at a specified offset from the fundamental.
By investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the entire
time record of the signal. It is mathematically possible to calculate an
expected bit error rate given a phase noise plot.
Offset Frequency (Hz)
As with most timing specifications, phase noise measurements have
issues relating to the limitations of the measurement equipment. The
noise floor of the equipment can be higher or lower than the noise
floor of the device. Additive phase noise is dependent on both the
noise floor of the input source and measurement equipment.
Additive phase jitter was measured with a Wenzel 156.25MHz
oscillator as the input source.
REVISION 1 08/03/15
7 DUAL 1:4, LVDS OUTPUT FANOUT BUFFER

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