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8SLVP2108 PDF 데이터시트 : 부품 기능 및 핀배열

부품번호 8SLVP2108
기능 LVPECL Output Fanout Buffer
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8SLVP2108 데이터시트, 핀배열, 회로
Low Phase Noise, Dual 1-to-8, 3.3V,
2.5V LVPECL Output Fanout Buffer
8SLVP2108
Datasheet
General Description
The 8SLVP2108 is a high-performance differential dual 1:8
LVPECL fanout buffer. The device is designed for the fanout of
high-frequency, very low additive phase-noise clock and data
signals. The 8SLVP2108 is characterized to operate from a 3.3V or
2.5V power supply. Guaranteed output-to-output and part-to-part
skew characteristics make the 8SLVP2108 ideal for those clock
distribution applications demanding well-defined performance and
repeatability. Two independent buffers with eight low skew outputs
each are available. The integrated bias voltage references enable
easy interfacing of single-ended signals to the device inputs. The
device is optimized for low power consumption and low additive
phase noise.
Block Diagram
PCLKA
nPCLKA
VCC
VREFA
Voltage
Reference
PCLKB
nPCLKB
VCC
VREFB
Voltage
Reference
QA0
nQA0
QA1
nQA1
QA2
nQA2
 
 
 
 
QA7
nQA7
QB0
nQB0
QB1
nQB1
QB2
nQB2
 
 
 
 
QB7
nQB7
Features
Two 1:8, low skew, low additive jitter LVPECL fanout buffers
Two differential clock inputs
Differential PCLKA, nPCLKA and PCLKB, nPCLKB pairs can
accept the following differential input levels: LVDS, LVPECL,
CML
Differential PCLKA, nPCLKA and PCLKB, nPCLKB pairs can
also accept single-ended LVCMOS levels. See Applications
section Wiring the Differential Input Levels to Accept
Single-ended Levels (Figure 1A and Figure 1B).
Maximum input clock frequency: 2GHz
Output bank skew: 15ps (typical)
Propagation delay: 390ps (maximum)
Low additive phase jitter, RMS: 54fs (maximum)
(fREF = 156.25MHz, VPP = 1V, 12kHz – 20MHz, VCC = 3.3V)
Full 3.3V and 2.5V supply voltage
Maximum device current consumption (IEE): 143mA
Available in Lead-free (RoHS 6), 48-Lead VFQFN package
Supports case temperature 105°C operations
-40°C to 85°C ambient operating temperature
Pin Assignment
VCC
QB3
nQB3
QB4
nQB4
QB5
nQB5
QB6
nQB6
QB7
nQB7
VCC
36 35 34 33 32 31 30 29 28 27 26 25
37 24
38 23
39 22
40 8SLVP2108 21
41 48-lead VFQFN 20
42 7mm x 7mm x 0.8mm 19
43 package body 18
44
45
NL Package
17
16
46 Top View 15
47 14
48 13
1 2 3 4 5 6 7 8 9 10 11 12
VCC
nQA4
QA4
nQA3
QA3
nQA2
QA2
nQA1
QA1
nQA0
QA0
VCC
©2016 Integrated Device Technology, Inc.
1
Revision B, November 21, 2016




8SLVP2108 pdf, 반도체, 판매, 대치품
8SLVP2108 Datasheet
Table 3C. LVPECL DC Characteristics, VCC = 3.3V ± 5%, VEE = 0V, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
Typical
IIH
Input High PCLKA, nPCLKA
Current PCLKB, nPCLKB
VCC = VIN = 3.465V
IIL
VREFx
Input Low PCLKA, PCLKB
Current nPCLKA, nPCLKB
Reference Voltage for Input
Bias
VCC = 3.465V, VIN = 0V
VCC = 3.465V, VIN = 0V
IREF = 2mA
-10
-150
VCC – 1.82
VCC – 1.48
VOH Output High Voltage; NOTE 1
VOL Output Low Voltage; NOTE 1
VCC – 1.25
VCC – 1.70
VCC – 1.00
VCC – 1.47
NOTE: VREFx denotes VREFA and VREFB.
NOTE 1: Outputs terminated with 50to VCC – 2V.
Maximum Units
150 µA
µA
µA
VCC – 1.27
VCC – 0.76
VCC – 1.25
V
V
V
Table 3D. LVPECL DC Characteristics, VCC = 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
IIH
Input High Current
PCLKA, nPCLKA
PCLKB, nPCLKB
VCC = VIN = 2.625V
IIL
VREFx
VOH
VOL
Input Low Current
PCLKA, PCLKB
nPCLKA, nPCLKB
Reference Voltage for Input Bias; NOTE 2
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
VCC = 2.625V, VIN = 0V
VCC = 2.625V, VIN = 0V
IREF = 2mA
-10
-150
VCC – 1.81
VCC – 1.26
VCC – 1.67
NOTE: VREFx denotes VREFA and VREFB.
NOTE 1: Outputs terminated with 50to VCC – 2V.
NOTE 2: For VCC < 3V, the use of an alternate bias voltage source is recommended.
Typical
VCC – 1.47
VCC – 1.00
VCC – 1.45
Maximum
150
VCC – 1.27
VCC – 0.75
VCC – 1.22
Units
µA
µA
µA
V
V
V
©2016 Integrated Device Technology, Inc.
4
Revision B, November 21, 2016

4페이지










8SLVP2108 전자부품, 판매, 대치품
8SLVP2108 Datasheet
Additive Phase Jitter
The spectral purity in a band at a specific offset from the fundamental
compared to the power of the fundamental is called the dBc Phase
Noise. This value is normally expressed using a Phase noise plot
and is most often the specified plot in many applications. Phase noise
is defined as the ratio of the noise power present in a 1Hz band at a
specified offset from the fundamental frequency to the power value of
the fundamental. This ratio is expressed in decibels (dBm) or a ratio
of the power in the 1Hz band to the power in the fundamental. When
the required offset is specified, the phase noise is called a dBc value,
which simply means dBm at a specified offset from the fundamental.
By investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the entire
time record of the signal. It is mathematically possible to calculate an
expected bit error rate given a phase noise plot.
Additive Phase Jitter @ 156.25MHZ, VPP = 1V
12kHz to 20MHz = 46fs (typical)
Offset from Carrier Frequency (Hz)
As with most timing specifications, phase noise measurements have
issues relating to the limitations of the equipment. Often the noise
floor of the equipment is higher than the noise floor of the device. This
is illustrated above. The device meets the noise floor of what is
shown, but can actually be lower. The phase noise is dependent on
the input source and measurement equipment.
Measured using a Wenzel 156.25MHz Oscillator as the input source.
©2016 Integrated Device Technology, Inc.
7
Revision B, November 21, 2016

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