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8T73S208A-01 PDF 데이터시트 : 부품 기능 및 핀배열

부품번호 8T73S208A-01
기능 LVPECL Clock Divider and Buffer
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8T73S208A-01 데이터시트, 핀배열, 회로
2.5V, 3.3V Differential LVPECL Clock
Divider and Buffer
REFER TO PCN# N1605-01, Effective Date August 18, 2016
FOR NEW DESIGNS USE PART NUMBER: 8T73S208B-01NLGI
8T73S208A-01
DATA SHEET
General Description
The 8T73S208A-01 is a high-performance differential LVPECL clock
divider and fanout buffer. The device is designed for the frequency
division and signal fanout of high-frequency, low phase-noise clocks.
The 8T73S208A-01 is characterized to operate from a 2.5V and 3.3V
power supply. Guaranteed output-to-output and part-to-part skew
characteristics make the 8T73S208A-01 ideal for those clock
distribution applications demanding well-defined performance and
repeatability. The integrated input termination resistors make
interfacing to the reference source easy and reduce passive
component count. Each output can be individually enabled or
disabled in the high-impedance state controlled by a I2C register. On
power-up, all outputs are disabled.
Features
One differential input reference clock
Differential pair can accept the following differential input
levels: LVDS, LVPECL, CML
Integrated input termination resistors
Eight LVPECL outputs
Selectable clock frequency division of ÷1, ÷2, ÷4 and ÷8
Maximum input clock frequency: 1GHz
LVCMOS interface levels for the control inputs
Individual output enable/disabled by I2C interface
Power-up state: all outputs disabled
Output skew: 60ps (maximum)
Output rise/fall times: 350ps (maximum)
Low additive phase jitter, RMS: 182fs (typical)
Full 2.5V and 3.3V supply voltages
Lead-free (RoHS 6) 32-Lead VFQFN packaging
-40°C to 85°C ambient operating temperature
8T73S208A-01 REVISION 2 05/20/16
1 ©2016 Integrated Device Technology, Inc.




8T73S208A-01 pdf, 반도체, 판매, 대치품
8T73S208A-01 DATA SHEET
Function Tables
Input Frequency Divider Operation
The FSEL1 and FSEL0 control pins configure the input frequency
divider. In the default state (FSEL[1:0] are set to logic 0:0 or left open)
the output frequency is equal to the input frequency (divide-by-1).
The other FSEL[1:0] settings configure the input divider to
divide-by-2, 4 or 8, respectively.
Table 3A. FSEL[1:0] Input Selection Function Table
variable bits which are set by the hardware pins ADR[1:0] (binary
11010, ADR1, ADR0). Bit 0 of slave address is used by the bus
controller to select either the read or write mode. The hardware pins
ADR1 and ADR0 and should be individually set by the user to avoid
address conflicts of multiple 8T73S208A-01 devices on the same
bus.
Table 3D. I2C Slave Address
Input
FSEL1
FSEL0
Operation
0 (default)
0
1
1
0 (default)
1
0
1
fQ[7:0] = fREF ÷ 1
fQ[7:0] = fREF ÷ 2
fQ[7:0] = fREF ÷ 4
fQ[7:0] = fREF ÷ 8
NOTE: FSEL1, FSEL0 are asynchronous controls
76543210
1 1 0 1 0 ADR1 ADR0 R/W
SCL
SDA
Output Enable Operation
The output enable/disable state of each individual differential output
Qx, nQx can be set by the content of the I2C register (see Table 3C).
A logic zero to an I2C bit in register 0 enables the corresponding
differential output, while a logic one disables the differential output
(see Table 3B). After each power cycle, the device resets all I2C bits
(Dn) to its default state (logic 1) and all Qx, nQx outputs are disabled.
After the first valid I2C write, the output enable state is controlled by
the I2C register. Setting and changing the output enable state through
the I2C interface is asynchronous to the input reference clock.
Table 3B. Individual Output Enable Control
Bit
Dn Operation
0 Output Qx, nQx is enabled.
START
Valid Data
Acknowledge
Figure 1: Standard I2C Transaction
STOP
START (S) – defined as high-to-low transition on SDA while holding
SCL HIGH.
DATA – between START and STOP cycles, SDA is synchronous with
SCL. Data may change only when SCL is LOW and must be stable
when SCL is HIGH.
ACKNOWLEDGE (A) – SDA is driven LOW before the SCL rising
edge and held LOW until the SCL falling edge.
STOP (S) – defined as low-to-high transition on SDA while holding
SCL HIGH
1 (default)
Output Qx, nQx is disabled in high-impedance
state.
Table 3C. Individual output enable control
S DevAdd W A Data Byte A P
Figure 2: Write Transaction
Bit D7 D6 D5 D4 D3 D2 D1 D0
Output Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0
Default 1 1 1 1 1 1 1 1
I2C Interface Protocol
The 8T73S208A-01 uses an I2C slave interface for writing and
reading the device configuration to and from the on-chip
configuration registers. This device uses the standard I2C write
format for a write transaction, and a standard I2C read format for a
read transaction. Figure 1 defines the I2C elements of the standard
I2C transaction. These elements consist of a start bit, data bytes, an
acknowledge or Not-Acknowledge bit and the stop bit. These
elements are arranged to make up the complete I2C transactions as
shown in Figure 2 and Figure 3. Figure 2 is a write transaction while
Figure 3 is read transaction. The 7-bit I2C slave address of the
8T73S208A-01 is a combination of a 5-bit fixed addresses and two
S DevAdd R A Data Byte
Figure 3: Read Transaction
AP
S
W
R
A
DevAdd
P
Start or Repeated Start
R/W is set for Write
R/W is set for Read
Ack
7 bit Device Address
Stop
2.5V, 3.3V DIFFERENTIAL LVPECL CLOCK DIVIDER AND BUFFER
4
REVISION 2 05/20/16

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8T73S208A-01 전자부품, 판매, 대치품
8T73S208A-01 DATA SHEET
Table 4D. LVPECL DC Characteristics, VCC = VCCO = 3.3V ± 5%, VEE = 0V, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
Typical
VOH Output High Voltage1
VOL Output Low Voltage1
VCCO – 1.102
VCCO – 1.802
VCCO – 0.95
VCCO – 1.6
VSWING
Peak-to-Peak
Output Voltage Swing
0.6 0.7
NOTE 1: Outputs terminated with 50to VCCO – 2V.
Maximum
VCCO – 0.775
VCCO – 1.367
1.0
Units
V
V
V
Table 4E. LVPECL DC Characteristics, VCC = VCCO = 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
Typical
VOH Output High Voltage1
VCCO – 1.125 VCCO – 0.95
VOL Output Low Voltage
VCCO – 1.799 VCCO – 1.6
VSWING
Peak-to-Peak
Output Voltage Swing
0.60 0.65
NOTE 1: Outputs terminated with 50to VCCO – 2V.
Maximum
VCCO – 0.767
VCCO – 1.359
1.00
Units
V
V
V
REVISION 2 05/20/16
7 2.5V, 3.3V DIFFERENTIAL LVPECL CLOCK DIVIDER AND BUFFER

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8T73S208A-01

LVPECL Clock Divider and Buffer

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