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8T73S208B-01 PDF 데이터시트 : 부품 기능 및 핀배열

부품번호 8T73S208B-01
기능 LVPECL Clock Divider and Fanout Buffer
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8T73S208B-01 데이터시트, 핀배열, 회로
2.5 V, 3.3 V Differential LVPECL Clock
Divider and Fanout Buffer
8T73S208B-01
Datasheet
General Description
The 8T73S208B-01 is a high-performance differential LVPECL clock
divider and fanout buffer. The device is designed for the frequency
division and signal fanout of high-frequency, low phase-noise clocks.
The 8T73S208B-01 is characterized to operate from a 2.5V and 3.3V
power supply. Guaranteed output-to-output and part-to-part skew
characteristics make the 8T73S208B-01 ideal for those clock
distribution applications demanding well-defined performance and
repeatability. The integrated input termination resistors make
interfacing to the reference source easy and reduce passive
component count. Each output can be individually enabled or
disabled in the high-impedance state controlled by a I2C register. On
power-up, all outputs are disabled.
Features
One differential input reference clock
Differential pair can accept the following differential input
levels: LVDS, LVPECL, CML
Integrated input termination resistors
Eight LVPECL outputs
Selectable clock frequency division of ÷1, ÷2, ÷4 and ÷8
Maximum input clock frequency: 1GHz
LVCMOS interface levels for the control inputs
Individual output enable/disabled by I2C interface
Power-up state: all outputs disabled
Output skew: 60ps (maximum)
Output rise/fall times: 350ps (maximum)
Low additive phase jitter, RMS: 182fs (typical)
Full 2.5V and 3.3V supply voltages
Lead-free (RoHS 6) 32-Lead VFQFN packaging
-40°C to 85°C ambient operating temperature
Block Diagram
IN
nIN
50
fREF
÷1, ÷2,
÷4, ÷8
50
VT
FSEL[1:0]
Pulldown (2)
2
SDA
SCL
Pullup
Pullup
I2C 8
ADR[1:0]
Pulldown (2)
2
Pin Assignment
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
Q5
nQ5
Q6
nQ6
ADR1
VEE
Q0
nQ0
Q1
nQ1
VEE
VCCO
32 31 30 29 28 27 26 25
1 24
2 23
3 22
4 21
5 20
6 19
7 18
8 17
9 10 11 12 13 14 15 16
FSEL0
VEE
nQ7
Q7
nQ6
Q6
VEE
VCCO
Q7
nQ7
5mm x 5mm, 32-pin VFQFN
©2016 Integrated Device Technology, Inc.
1
April 28, 2016




8T73S208B-01 pdf, 반도체, 판매, 대치품
8T73S208B-01 Datasheet
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress
specifications only. Functional operation of the product at these conditions or any conditions beyond those listed in the DC Characteristics or
AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Item
Supply Voltage, VCC
Inputs, VI
Input Termination Current, IVT
Outputs, IO (LVPECL)
Continuous Current
Surge Current
Storage Temperature, TSTG
Maximum Junction Temperature, TJMAX
ESD - Human Body Model1
ESD - Charged Device Model
Rating
4.6V
-0.5V to VCC + 0.5V
±35mA
50mA
100mA
-65C to 150C
125°C
2000V
500V
NOTE 1:According to JEDEC/JS-001-2012/JESD22-C101E.
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, VCC = VCCO = 2.5V ± 5% or 3.3V ± 5%, VEE = 0V, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VCC
VCC
VCCO
VCCO
IEE
Power Supply Voltage
Power Supply Voltage
Output Supply Voltage
Output Supply Voltage
Power Supply Current
2.375
3.135
2.375
3.135
2.5V
3.3V
2.5V
3.3V
92
2.625
3.465
2.625
3.465
110
V
V
V
V
mA
©2016 Integrated Device Technology, Inc.
4
April 28, 2016

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8T73S208B-01 전자부품, 판매, 대치품
8T73S208B-01 Datasheet
AC Electrical Characteristics
Table 5. AC Electrical Characteristics, VCC = VCCO = 2.5V ± 5% or 3.3V ± 5%, TA = -40°C to 85°C
Symbol Parameter1
Test Conditions
Minimum Typical
Maximum
Units
fREF Input Frequency IN, nIN
fSCL I2C Clock Frequency
Buffer Additive Phase Jitter,
tJIT
RMS; refer to Additive Phase
Jitter Section, measured with
fREF =156.25MHz,
Integration Range: 12kHz – 20MHz
FSEL[1:0] = 00
1 GHz
400 kHz
182 207 fs
FSEL[1:0] = 00
350
750 ps
tPD
Propagation Delay2
IN, nIN to
Qx, nQx
FSEL[1:0] = 01
FSEL[1:0] = 10
500
550
870
1052
ps
ps
tsk(o)
Output Skew3, 4
FSEL[1:0] = 11
650
1230
60
ps
ps
tsk(p)
tsk(pp)
Pulse Skew
Part-to-Part Skew3, 5, 6
50 ps
500 ps
Any Frequency
50 %
odc Output Duty Cycle7
at fREF = 100MHz
at fREF = 125MHz
48 50 52 %
48 50 52 %
at fREF = 156.25MHz
48 50 52 %
tPDZ
Output Enable and Disable
Time8
Output Enable/ Disable State from/ to
Active/ Inactive
1
µs
tR / tF
Output Rise/Fall Time
20% to 80%
10% to 90%
140 205 ps
180 350 ps
NOTE 1: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device
is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal
equilibrium has been reached under these conditions.
NOTE 2: Measured from the differential input crossing point to the differential output cross point.
NOTE 3:Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential cross point.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 5: Defined as skew between outputs on different devices operating at the same supply voltage, same temperature, same frequency and
with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cross point.
NOTE 6: Part-to-part skew specification does not guarantee divider synchronization among devices.
NOTE 7: If FSEL[1:0] = 00 (divide-by-one), the output duty cycle will depend on the input duty cycle.
NOTE 8: Measured from SDA rising edge of I2C stop command.
©2016 Integrated Device Technology, Inc.
7
April 28, 2016

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8T73S208B-01

LVPECL Clock Divider and Fanout Buffer

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