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부품번호 8T74S208A-01
기능 2.5V Differential LVDS Clock Divider and Fanout Buffer
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8T74S208A-01 데이터시트, 핀배열, 회로
2.5V Differential LVDS Clock Divider and
Fanout Buffer
8T74S208A-01
REFER TO PCN# N1608-01, Effective Date November 18, 2016
FOR NEW DESIGNS USE PART NUMBER 8T74S208C-01
DATA SHEET
General Description
The 8T74S208A-01 is a high-performance differential LVDS clock
divider and fanout buffer. The device is designed for the frequency
division and signal fanout of high-frequency, low phase-noise clocks.
The 8T74S208A-01 is characterized to operate from a 2.5V power
supply. Guaranteed output-to-output and part-to-part skew
characteristics make the 8T74S208A-01 ideal for those clock
distribution applications demanding well-defined performance and
repeatability. The integrated input termination resistors make
interfacing to the reference source easy and reduce passive
component count. Each output can be individually enabled or
disabled in the high-impedance state controlled by a I2C register. On
power-up, all outputs are disabled.
Features
One differential input reference clock
Differential pair can accept the following differential input levels:
LVDS, LVPECL, CML
Integrated input termination resistors
Eight LVDS outputs
Selectable clock frequency division of ÷1, ÷2, ÷4 and ÷8
Maximum input clock frequency: 1GHz
LVCMOS interface levels for the control inputs
Individual output enabled/ disabled by I2C interface
Output skew: 45ps (maximum)
Output rise/fall times: 370ps (maximum)
Low additive phase jitter, RMS: 96fs (typical)
Full 2.5V supply voltage
Outputs disable at power up
Lead-free (RoHS 6) 32-Lead VFQFN packaging
-40°C to 85°C ambient operating temperature
Block Diagram
IN
nIN
50
fREF
÷1, ÷2,
÷4, ÷8
50
VT
FSEL[1:0] Pulldown (2)
2
SDA Pullup
SCL Pullup
ADR[1:0] Pulldown (2)
2
I2C
8
Pin Assignment
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
Q5
nQ5
Q6
nQ6
ADR1
GND
Q0
nQ0
Q1
nQ1
GND
VDDO
32 31 30 29 28 27 26 25
1 24
2 23
3 22
4 21
8T74S208A-01
5 20
6 19
7 18
8 17
9 10 11 12 13 14 15 16
FSEL0
GND
nQ7
Q7
nQ6
Q6
GND
VDDO
Q7 8T74S208A-01
nQ7
32-Lead VFQFN, 5mm x 5mm x 0.925mm
8T74S208A-01 REVISION 2 08/17/16
1 ©2016 Integrated Device Technology, Inc.




8T74S208A-01 pdf, 반도체, 판매, 대치품
8T74S208A-01 DATA SHEET
Function Tables
Input Frequency Divider Operation
The FSEL1 and FSEL0 control pins configure the input frequency
divider. In the default state (FSEL[1:0] are set to logic 0:0 or left open)
the output frequency is equal to the input frequency (divide-by-1).
The other FSEL[1:0] settings configure the input divider to
divide-by-2, 4 or 8, respectively.
Table 3A. FSEL[1:0] Input Selection Function Table1
Input
FSEL1
FSEL0 Operation
0 (default)
0 (default) fQ[7:0] = fREF ÷ 1
0 1 fQ[7:0] = fREF ÷ 2
1 0 fQ[7:0] = fREF ÷ 4
1 1 fQ[7:0] = fREF ÷ 8
NOTE 1: FSEL1, FSEL0 are asynchronous controls
Output Enable Operation
The output enable/disable state of each individual differential output
Qx, nQx can be set by the content of the I2C register (see Table 3C).
A logic zero to an I2C bit in register 0 enables the corresponding
differential output, while a logic one disables the differential output
(see Table 3B). After each power cycle, the device resets all I2C bits
(Dn) to its default state (logic 1) and all Qx, nQx outputs are disabled.
After the first valid I2C write, the output enable state is controlled by
the I2C register. Setting and changing the output enable state through
the I2C interface is asynchronous to the input reference clock.
Table 3B. Individual Output Enable Control
Bit
Dn
0
1 (default)
Operation
Output Qx, nQx is enabled.
Output Qx, nQx is disabled in high-impedance
state.
Table 3C. Individual Output Enable Control
Bit D7 D6 D5 D4 D3 D2 D1 D0
Output Q7 Q6 Q5 Q4 Q3 Q2 Q1 Q0
Default 1 1 1 1 1 1 1 1
I2C Interface Protocol
The 8T74S208A-01 uses an I2C slave interface for writing and
reading the device configuration to and from the on-chip
configuration registers. This device uses the standard I2C write
format for a write transaction, and a standard I2C read format for a
read transaction. Figure 1 defines the I2C elements of the standard
I2C transaction. These elements consist of a start bit, data bytes, an
acknowledge or Not-Acknowledge bit and the stop bit. These
elements are arranged to make up the complete I2C transactions as
shown in Figure 1 and Figure 2. Figure 1 is a write transaction while
Figure 2 is read transaction. The 7-bit I2C slave address of the
8T74S208A-01 is a combination of a 5-bit fixed addresses and two
variable bits which are set by the hardware pins ADR[1:0] (binary
11010, ADR1, ADR0). Bit 0 of slave address is used by the bus
controller to select either the read or write mode. The hardware pins
ADR1 and ADR0 and should be individually set by the user to avoid
address conflicts of multiple 8T74S208A-01 devices on the same
bus.
Table 3D. I2C Slave Address
7654321 0
1 1 0 1 0 ADR1 ADR0 R/W
SCL
SDA
START
Valid Data
Acknowledge
Figure 1. Standard I2C Transaction
STOP
START (S) – defined as high-to-low transition on SDA while holding
SCL HIGH.
DATA – between START and STOP cycles, SDA is synchronous with
SCL. Data may change only when SCL is LOW and must be stable
when SCL is HIGH.
ACKNOWLEDGE (A) – SDA is driven LOW before the SCL rising
edge and held LOW until the SCL falling edge.
STOP (S) – defined as low-to-high transition on SDA while holding
SCL HIGH
S DevAdd W A Data Byte A P
Figure 2. Read Transaction
S DevAdd R A Data Byte
Figure 3. Read Transaction
S – Start or Repeated Start
W – R/W is set for Write
R – R/W is set for Read
A – Ack
DevAdd –7 bit Device Address
P – Stop
AP
2.5V DIFFERENTIAL LVDS CLOCK DIVIDER AND FANOUT BUFFER
4
REVISION 2 08/17/16

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8T74S208A-01 전자부품, 판매, 대치품
8T74S208A-01 DATA SHEET
AC Electrical Characteristics
Table 5. AC Electrical Characteristics, VDD = VDDO = 2.5V ± 5%, TA = -40°C to 85°C1
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum Units
Input
fREF Frequency IN, nIN
fSCL I2C Clock Frequency
Buffer Additive Phase Jitter,
RMS; refer to Additive Phase
fREF =156.25,
tJIT
Jitter Section, measured with
Integration Range:
12kHz – 20MHz
FSEL[1:0] = 00
1 GHz
400 kHz
96 120 fs
FSEL[1:0] = 00
420
620 ps
tPD
Propagation IN, nIN to
Delay2
Qx, nQx
FSEL[1:0] = 01
FSEL[1:0] = 10
580
680
800 ps
920 ps
tsk(o)
Output Skew3, 4
FSEL[1:0] = 11
780
1050
45
ps
ps
tsk(p)
tsk(pp)
Pulse Skew
Part-to-Part Skew4, 5, 6
FSEL[1:0] = 00
55 ps
200 ps
FSEL[1:0] = 00
50 %
odc Output Duty Cycle7
FSEL[1:0] = 01
FSEL[1:0] = 10
48 50 52 %
48 50 52 %
FSEL[1:0] = 11
48 50 52 %
Output Enable and
Output Enable/ Disable State
tPDZ Disable Time8
from/ to Active/ Inactive
1 µs
tR / tF
Output Rise/ Fall Time
20% to 80%
10% to 90%
155 230 ps
245 350 ps
NOTE 1: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the
device is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications
after thermal equilibrium has been reached under these conditions.
NOTE 2: Measured from the differential input crosspoint to the differential output crosspoint.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at the differential crosspoint.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 5: Defined as skew between outputs on different devices operating at the same supply voltage, same temperature, same frequency
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at the differential cros-
spoint.
NOTE 6: Part-to-part skew specification does not guarantee divider synchronization among devices.
NOTE 7: If FSEL[1:0] = 00 (divide-by-one), the output duty cycle will depend on the input duty cycle.
NOTE 8: Measured from SDA rising edge of I2C stop command.
REVISION 2 08/17/16
7 2.5V DIFFERENTIAL LVDS CLOCK DIVIDER AND FANOUT BUFFER

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8T74S208A-01

2.5V Differential LVDS Clock Divider and Fanout Buffer

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