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부품번호 8T74S208
기능 2.5V Differential LVDS Clock Divider and Fanout Buffer
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8T74S208 데이터시트, 핀배열, 회로
2.5V Differential LVDS Clock Divider
and Fanout Buffer
8T74S208
DATA SHEET
General Description
The 8T74S208 is a high-performance differential LVDS clock divider
and fanout buffer. The device is designed for the frequency division
and signal fanout of high-frequency, low phase-noise clocks. The
8T74S208 is characterized to operate from a 2.5V power supply.
Guaranteed output-to-output and part-to-part skew characteristics
make the 8T74S208 ideal for those clock distribution applications
demanding well-defined performance and repeatability. The
integrated input termination resistors make interfacing to the
reference source easy and reduce passive component count. Each
output can be individually enabled or disabled in the high-impedance
state controlled by a I2C register. On power-up, all outputs are
enabled.
Features
• One differential input reference clock
• Differential pair can accept the following differential input
levels: LVDS, LVPECL, CML
• Integrated input termination resistors
• Eight LVDS outputs
• Selectable clock frequency division of ÷1, ÷2, ÷4 and ÷8
• Maximum input clock frequency: 1GHz
• LVCMOS interface levels for the control inputs
• Individual output enabled/ disabled by I2C interface
• Output skew: 45ps (maximum)
• Output rise/fall times: 350ps (maximum)
• Low additive phase jitter, RMS: 96fs (typical)
• Full 2.5V supply voltage
• Outputs enabled at power up
• Lead-free (RoHS 6) 32-Lead VFQFN packaging
• -40°C to 85°C ambient operating temperature
Block Diagram
IN
nIN
50
fREF
÷1, ÷2,
÷4, ÷8
50
VT
FSEL[1:0] Pulldown (2)
2
SDA Pullup
SCL Pullup
ADR[1:0] Pulldown (2)
2
I2C
8
Pin Assignment
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
nQ4
Q5
nQ5
Q6
nQ6
ADR1
GND
Q0
nQ0
Q1
nQ1
GND
VDDO
 
32 31 30 29 28 27 26 25
1 24
2 23
3 22
4 21
8T74S208
5 20
6 19
7 18
8 17
9 10 11 12 13 14 15 16
FSEL0
GND
nQ7
Q7
nQ6
Q6
GND
VDDO
Q7 32-Lead VFQFN
nQ7 5mm x 5mm x 0.925mm
package body
NL Package, Top View
8T74S208 REVISION 1 09/10/14
1 ©2014 Integrated Device Technology, Inc.




8T74S208 pdf, 반도체, 판매, 대치품
8T74S208 DATA SHEET
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress
specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC Electrical Characteristics
or AC Electrical Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product
reliability.
Item
Supply Voltage, VCC
Inputs, VI
Input Termination Current, IVT
Outputs, IO (LVDS)
Continuous Current
Surge Current
Storage Temperature, TSTG
Maximum Junction Temperature, TJMAX
ESD - Human Body Model 1
ESD - Charged Device Model 1
NOTE: 1. According to JEDEC/JS-001-2012/JESD22-C101E.
Rating
4.6V
-0.5V to VDD + 0.5V
±35mA
10mA
15mA
-65C to 150C
125°C
2000V
500V
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, VDD = VDDO = 2.5V ± 5%, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum Typical
VDD
VDDO
IDD
IDDO
Power Supply Voltage
Output Supply Voltage
Power Supply Current
Output Supply Current
2.375
2.375
All Outputs are Enabled and Terminated
2.5V
2.5V
41
153
.
Maximum
2.625
2.625
49
176
Units
V
V
mA
mA
Table 4B. LVCMOS/LVTTL Input DC Characteristics, VDD = VDDO = 2.5V ± 5%, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum Typical
VIH Input High Voltage1
VIL Input Low Voltage1
1.7
-0.3
FSEL[1:0],
IIH
Input
ADR[1:0]
High Current
SCL, SDA
VDD = VIN = 2.625
VDD = VIN = 2.625
FSEL[1:0],
IIL
Input
Low Current
ADR[1:0]
SCL, SDA
VDD = 2.625, VIN = 0V
VDD = 2.625, VIN = 0V
-10
-150
NOTE: 1. VIL should not be lower than -0.3V and VIH should not be higher than VDD + 0.3V.
Maximum
VDD + 0.3
0.7
150
5
Units
V
V
µA
µA
µA
µA
2.5V DIFFERENTIAL LVDS CLOCK DIVIDER AND FANOUT BUFFER
4
REVISION 1 09/10/14

4페이지










8T74S208 전자부품, 판매, 대치품
8T74S208 DATA SHEET
Additive Phase Jitter
The spectral purity in a band at a specific offset from the fundamental
compared to the power of the fundamental is called the dBc Phase
Noise. This value is normally expressed using a Phase noise plot
and is most often the specified plot in many applications. Phase noise
is defined as the ratio of the noise power present in a 1Hz band at a
specified offset from the fundamental frequency to the power value of
the fundamental. This ratio is expressed in decibels (dBm) or a ratio
Typical Phase Jitter at 156.25MHz
of the power in the 1Hz band to the power in the fundamental. When
the required offset is specified, the phase noise is called a dBc value,
which simply means dBm at a specified offset from the fundamental.
By investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the entire
time record of the signal. It is mathematically possible to calculate an
expected bit error rate given a phase noise plot.
Additive Phase Jitter: 96fs (typical)
The input source is 156.25MHz Wenzel Oscillator.
Offset from Carrier Frequency (Hz)
REVISION 1 09/10/14
7 2.5V DIFFERENTIAL LVDS CLOCK DIVIDER AND FANOUT BUFFER

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