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8V79S680 PDF 데이터시트 : 부품 기능 및 핀배열

부품번호 8V79S680
기능 JESD204B Compliant Fanout Buffer and Divider
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8V79S680 데이터시트, 핀배열, 회로
JESD204B Compliant Fanout Buffer
and Divider
8V79S680
Datasheet
Description
The 8V79S680 is a fully integrated, clock and SYSREF signal fanout
buffer for JESD204B applications. It is designed as a high-performance
clock and converter synchronization solution for wireless base station
radio equipment boards with JESD204B subclass 0, 1 and 2
compliance. The main function of the device is the distribution and
fanout of high-frequency clocks and low-frequency system reference
signals generated by a JESB204B clock generator such as the IDT
8V19N480, extending its fanout capabilities and providing additional
phase-delay. The 8V79S680 is optimized to deliver very low phase noise
clocks and precise, phase-adjustable SYSREF synchronization signals
as required in GSM, WCDMA, LTE, LTE-A radio board implementations.
Low-skew outputs, low device-to-device skew characteristics and fast
output rise/fall times help the system design to achieve deterministic
clock and SYSREF phase relationship across devices.
The device distributes the input clock (CLK) and JESD204B SYSREF
signals (REF) to four fanout channels. In each channel, both input clock
and SYSREF signals are fanned-out to multiple clock (QCLK) and
SYSREF (QREF) outputs. Clock signals can be frequency-divided in
each channel. Configurable phase-delay circuits are available for both
clock and SYSREF signals. The propagation delays in all signal paths
are fully deterministic to support fixed phase relationships between clock
and SYSREF signals within one device. Clock divider can be bypassed
for low-latency clock paths. The device facilitates synchronization
between frequency dividers within the device and across multiple
devices, removing phase ambiguity introduced in dividers between
power and configuration cycles.
Each channel supports clock frequencies up to 3GHz. In an alternative
configuration, for instance JESD204B subclass 0 and 2, the SYSREF
(QREF) outputs can be configured as regular clock outputs adding
additional clock fanout to the device.
All outputs are very flexible in amplitude configuration, output signal
termination and allow both DC and AC coupling. Outputs can be
disabled and powered-down when not used. The SYSREF output
pre-bias feature supports prevention of power-on glitches and enables
AC-coupling of the system synchronization signals.
The device is configured through a 3-wire SPI serial interface. The
device is packaged in a lead-free (RoHS 6) 64-lead VFQFN package.
The extended temperature range supports wireless infrastructure,
telecommunication and networking end equipment requirements. The
device is a member of the high-performance clock family from IDT.
Features
Supports high-speed, low phase noise converter clocks
Distribution, fanout, phase-delay of clock and SYSREF signals
Very low output noise floor: -158.8dBc/Hz noise floor
(245.76MHz)
Supports clock frequencies up to 3GHz, including clock output
frequencies of 983.04MHz, 491.52MHz, 245.76MHz and
122.88MHz
4 output channels with a total of 16 differential outputs, organized
in:
— 8 dedicated clock outputs
— 8 outputs configurable as SYSREF outputs with individual
phase delay stages, or configurable as additional clock outputs
Each channel contains:
— frequency dividers: ÷1, ÷2, ÷4, ÷6, ÷8, ÷12, ÷16
— clock phase delay circuits
Clock phase delay circuits
— Clock: delay unit is the clock period; 256 steps
— SYSREF: Configurable precision phase delay circuits: 8 steps
of 131ps, 262ps, 393ps or 524ps
Flexible differential outputs:
— LVDS/LVPECL configurable
— Amplitude configurable
— Power-down modes for unused outputs
— Supports DC and AC coupling
— QREF (SYSREF) output pre-bias feature to prevent glitches
when turning output on or off
Supply voltage:
— 3.3V core and signal I/O
— 1.8V Digital control SPI I/O (3.3V-tolerant inputs)
64 VFQFN-P package (9mm x 9mm x 0.85mm)
Ambient temperature range: -40°C to +85°C
Typical Applications
JESD204B low phase noise clock and SYSREF signal distribution
Supports JESD204 subclass 0, 1 and 2
Clock distribution device for jitter-sensitive ADC and DAC circuits
Wireless infrastructure
Radar and imaging
Instrumentation and medical
©2016 Integrated Device Technology, Inc.
1
August 4, 2016




8V79S680 pdf, 반도체, 판매, 대치품
Pin Descriptions
Table 1: Pin Descriptions
Number
Name
Typea
1,
2
QREF_B0,
nQREF_B0
Output
3,
4
QREF_B1,
nQREF_B1
Output
5 VDD_QREFB Power
6 VDD_QCLKB Power
7,
8
QCLK_B0,
nQCLK_B0
Output
9,
10
QCLK_B1,
nQCLK_B1
Output
11 VDD_QCLKB Power
12 VDD_QREFC Power
13,
14
QREF_C0,
nQREF_C0
Output
15,
16
QREF_C1,
nQREF_C1
Output
17 VDD_QREFC Power
18 VDD_QCLKC Power
19,
20
QCLK_C0,
nQCLK_C0
Output
21,
22
QCLK_C1,
nQCLK_C1
Output
23 VDD_QCLKC Power
24 VDD_QREFD Power
25,
26
QREF_D,
nQREF_D
Output
27 VDD_QREFD Power
28 VDD_QCLKD Power
29,
30
QCLK_D,
nQCLK_D
Output
31 VDD_QCLKD Power
32 VDD_QREFA01 Power
33,
34
nQREF_A0,
QREF_A0
Output
35,
36
nQREF_A1,
QREF_A1
Output
8V79S680 Datasheet
Description
Differential SYSREF/clock output QREF_B0. LVDS style for SYSREF operation,
configurable LVPECL/LVDS style and amplitude for clock operation.
Differential SYSREF/clock output QREF_B1. LVDS style for SYSREF operation,
configurable LVPECL/LVDS style and amplitude for clock operation.
Positive supply voltage (3.3V) for the QREF_B[1:0] outputs.
Positive supply voltage (3.3V) for the QCLK_B[1:0] outputs.
Differential clock output QCLK_B0. Configurable LVPECL/LVDS style and amplitude.
Differential clock output QCLK_B1. Configurable LVPECL/LVDS style and amplitude.
Positive supply voltage (3.3V) for the QCLK_B[1:0] outputs.
Positive supply voltage (3.3V) for the QREF_C[1:0] outputs.
Differential SYSREF/clock output QREF_C0. LVDS style for SYSREF operation,
configurable LVPECL/LVDS style and amplitude for clock operation.
Differential SYSREF/clock output QREF_C1. LVDS style for SYSREF operation,
configurable LVPECL/LVDS style and amplitude for clock operation.
Positive supply voltage (3.3V) for the QREF_C[1:0] outputs.
Positive supply voltage (3.3V) for the QCLK_C[1:0] outputs.
Differential clock output QCLK_C0. Configurable LVPECL/LVDS style and amplitude.
Differential clock output QCLK_C1. Configurable LVPECL/LVDS style and amplitude.
Positive supply voltage (3.3V) for the QCLK_C[1:0] outputs.
Positive supply voltage (3.3V) for the QREF_D outputs.
Differential SYSREF/clock output QREF_D. LVDS style for SYSREF operation,
configurable LVPECL/LVDS style and amplitude for clock operation.
Positive supply voltage (3.3V) for the QREF_D outputs.
Positive supply voltage (3.3V) for the QCLK_D outputs.
Differential clock output QCLK_D. Configurable LVPECL/LVDS style and amplitude.
Positive supply voltage (3.3V) for the QCLK_D outputs.
Positive supply voltage (3.3V) for the QREF_A[1:0] outputs.
Differential SYSREF/clock output QREF_A0. LVDS style for SYSREF operation,
configurable LVPECL/LVDS style and amplitude for clock operation.
Differential SYSREF/clock output QREF_A1. LVDS style for SYSREF operation,
configurable LVPECL/LVDS style and amplitude for clock operation.
©2016 Integrated Device Technology, Inc
4
August 4, 2016

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8V79S680 전자부품, 판매, 대치품
8V79S680 Datasheet
Phase Delay
Output phase delay is independently supported on each clock channel and each SYSREF output. The delay unit of the clock channel phase-delay
circuits CLK_x is a function of the frequency fIN applied to CLK input: 1 ÷ fIN.
The delay unit of the SYSREF phase-delay circuits REF_r is a function of an internal oscillator frequency fDCO and the DLC multiplier setting. The
oscillator is fully self-contained and located in delay calibration block (DCB). At startup, this oscillator is calibrated with the input frequency fIN as
reference. After the calibration, the oscillator is turned-off to save power and to eliminate noise. See Table 3 for details on the delay unit, number of
available steps and the delay range.
Table 3: Delay Circuit Characteristics
Delay Circuit
Clock channel CLK_x
Unit
1 ÷ fIN
1.017ns at fIN = 983.04MHz
TDCBb
Steps
256
Range
256 ÷ fIN a
0 to 259.3ns at fIN = 983.04MHz
0…7 * TDCBc
SYSREF REF_r
DLC = 0: 131ps
DLC = 1: 262ps
DLC = 2: 393ps
DLC = 3: 524ps
8
DLC = 0: 0 to 0.917ns
DLC = 1: 0 to 1.834ns
DLC = 2: 0 to 2.751ns
DLC = 3: 0 to 3.668ns
a. At fIN = 983.04MHz, the clock channel delay range is equal to 260.416ns and encompasses 32 periods of a 122.88MHz clock signal.
b. TDCB ~ DLC ÷ (8·fDCO). fDCO = 983.04MHz. DLC = 1, 2, 3 or 4.
c. SYSREF phase delay supports 8 delay stops within one input reference period for fIN = 254.76MHz to fIN = 983.04MHz.
Delay Calibration Block (DCB)
The DCB sets the SYSREF delay unit by providing a reference signal to the QREF_r delay circuits. Figure 3 shows the functional diagram. The DCB
requires configuration and calibration. Verification of the calibration is optional.
Description. The DCB consists of an internal DCO running at fDCO = 983.04±20MHz, three frequency dividers PDCB, MDCB and NDCB and a digital
hold circuit. The DCB input frequency is the device input frequency fIN at the differential CLK, nCLK input. The input frequency acts as a reference to
lock the oscillator to a stable and known frequency.
The output of the DCB is the effective delay unit TDCB which is approx. one eighth of the oscillator period multiplied by the DLC multiplier. The DLC
multiplier extends the delay unit by a factor of 1, 2, 3 or 4. For instance, at a DCO frequency of 983.04MHz, DLC = 1 sets the SYSREF delay unit to
131ps; DLC = 2 sets the delay unit to 262ps, etc.
Configuration. Select a desired delay unit and corresponding DLC multiplier from Table 4. DLC[1:0] also sets the NDCB divider. Then, find a PDCB
and MDCB divider configuration to locate the oscillator frequency into the range of fDCO = 983.04MHz according to the formula in Figure 3. The DCO
lock condition is f1 = f2 while both f1 and f2 must be lower than 200MHz. For instance, if fIN = 245.76MHz and the smallest possible SYSREF delay
unit is desired, set DLC = 1 (DLC[1:0] = 00; also sets NDCB = ÷1). Then, set PDCB = ÷24 and MDCB = ÷96. As a result, f1 = f2 = 10.24MHz, fDCO =
983.04MHz. This example configuration results in a delay unit of measured: 131ps. Figure 5 shows more configuration examples.
Calibration. Calibration requires a valid DCB configuration with the DCO locking to an input frequency. Setting DCB_CAL = 1 starts an automatic
calibration. At the end, the DCB_CAL bit will clear, the delay unit value is stored digitally and the DCO, PDCB, MDCB and NDCB frequency dividers turn
off. The QREF_r delay circuits now use the stored constant delay unit. The delay unit remains digitally stored until the next power cycle. The DCB
calibration must run once as part of the device startup procedure and must be re-run after each input frequency or DCB configuration change.
Verification. Verify a successful calibration by reading the DAC_CODE value. 0 < DAC_CODE< 32767 indicates a successful calibration. If
DAC_CODE = 0 or DAC_CODE = 32767, the DCB calibration should be re-run with an alternative PDCB, MDCB setting while maintaining the desired
MDCB · NDCB/PDCB ratio for locking the DCO to the input frequency.
©2016 Integrated Device Technology, Inc
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