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8V79S674 데이터시트 PDF




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부품번호 8V79S674 기능
기능 LVPECL Clock Divider and Fanout Buffer
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8V79S674 데이터시트, 핀배열, 회로
Differential-to-3.3V, 2.5V LVPECL
Clock Divider and Fanout Buffer
8V79S674
DATA SHEET
General Description
The 8V79S674 is a clock divider and fanout buffer. The device has
been designed for clock signal division in wireless base station radio
equipment boards. The device is optimized to deliver excellent
additive phase jitter performance. The 8V79S674 uses SiGe
technology for an optimum of high clock frequency and low phase
noise performance, combined with high power supply noise rejection.
The device offers the frequency division by ÷1, ÷2, ÷4 and ÷8. Four
low-skew LVPECL outputs are available and support clock output
frequencies up to 2500MHz (÷1 frequency division). Outputs can be
disabled to save power consumption if not used. The device is
packaged in a lead-free (RoHS 6) 20-lead VFQFN package. The
extended temperature range supports wireless infrastructure,
telecommunication and networking end equipment requirements.
Features
Clock signal division and distribution
SiGe technology for high-frequency and fast signal rise/fall times
Four low-skew LVPECL clock outputs
Supports frequency division of ÷1, ÷2, ÷4 and ÷8
Maximum frequency: 2500MHz
Maximum output skew: 50ps (maximum)
Maximum LVPECL output rise/fall time: 200ps (maximum)
3.3V or 2.5V core and output supply mode
Supports 1.8V I/O logic levels for all control pins
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package
Block Diagram
IN ÷N
nIN
2x 50
VT
VREFAC
Reference Voltage
N[1:0]
nOEA
nOEB
Pulldown
Pulldown
Pulldown
.
8V79S674 REVISION 2 04/10/15
Pin Assignment
Q0
nQ0
Q1
nQ1
15 14 13 12 11
VCC 16
10 Q3
Q0 17
9 nQ3
Q2
nQ2
Q3
nQ3
nQ0 18
nOEA 19
VEE 20
1
8V79S674
8 nOEB
7 N1
6 VEE
2 3 45
20-pin, 4mm x 4mm VFQFN Package
1 ©2015 Integrated Device Technology, Inc.




8V79S674 pdf, 반도체, 판매, 대치품
8V79S674 DATA SHEET
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress
specifications only. Functional operation of the product at these conditions or any conditions beyond those listed in the DC Characteristics or
AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Item
Supply Voltage, VCC
Inputs, VI
Outputs, IO
Continuous Current
Surge Current
Input Current, IN, nIN
VT Current, IVT
Input Sink/Source, IREF_AC
TJ
Storage Temperature, TSTG
Rating
4.6V
-0.5V to VCC + 0.5V
50mA
100mA
±50mA
±100mA
±2mA
125C
-65C to 150C
DC Electrical Characteristics
Table 4A. Power Supply DC Characteristics, VCC = 3.3V ± 5%, VEE = 0V, TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
Minimum
Typical
VCC Power Supply Voltage
IEE Power Supply Current
Outputs Unloaded
3.135
3.3
80
Maximum
3.465
90
Units
V
mA
Table 4B. Power Supply DC Characteristics, VCC = 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
Minimum
Typical
VCC Power Supply Voltage
IEE Power Supply Current
Outputs Unloaded
2.375
2.5
75
Maximum
2.625
85
Units
V
mA
Table 4C. LVCMOS/LVTTL DC Characteristics, VCC = 3.3V ± 5% or 2.5V ± 5%, VEE = 0V, TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum
VIH Input High Voltage
VCC = 3.3V
VCC = 2.5V
1.2
1.2
VIL Input Low Voltage
1.8V logic
-0.3
IIH
Input High
Current
N[1:0],
nOEA, nOEB
VCC = VIN = 3.465V or 2.625V
VCC
VCC
0.3
150
IIL
Input Low
Current
N[1:0],
nOEA, nOEB
VCC = 3.465V or 2.625V, VIN = 0V
-10
Units
V
V
V
µA
uA
DIFFERENTIAL-TO-3.3V, 2.5V LVPECL
CLOCK DIVIDER AND FANOUT BUFFER
4
REVISION 2 04/10/15

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8V79S674 전자부품, 판매, 대치품
8V79S674 DATA SHEET
Additive Phase Jitter
The spectral purity in a band at a specific offset from the fundamental
compared to the power of the fundamental is called the dBc Phase
Noise. This value is normally expressed using a Phase noise plot
and is most often the specified plot in many applications. Phase noise
is defined as the ratio of the noise power present in a 1Hz band at a
specified offset from the fundamental frequency to the power value of
the fundamental. This ratio is expressed in decibels (dBm) or a ratio
of the power in the 1Hz band to the power in the fundamental. When
the required offset is specified, the phase noise is called a dBc value,
which simply means dBm at a specified offset from the fundamental.
By investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the entire
time record of the signal. It is mathematically possible to calculate an
expected bit error rate given a phase noise plot.
Offset from Carrier Frequency (Hz)
As with most timing specifications, phase noise measurements have
issues relating to the limitations of the measurement equipment. The
noise floor of the equipment can be higher or lower than the noise
floor of the device. Additive phase noise is dependent on both the
noise floor of the input source and measurement equipment.
The additive phase jitter for this device was measured using a 156.25
MHz Wenzel oscillator as input clock source and an Agilent E5052
Phase noise analyzer.
REVISION 2 04/10/15
7 DIFFERENTIAL-TO-3.3V, 2.5V LVPECL
CLOCK DIVIDER AND FANOUT BUFFER

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8V79S674

LVPECL Clock Divider and Fanout Buffer

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