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PDF 8V74S4622 Data sheet ( Hoja de datos )
| Número de pieza | 8V74S4622 | |
| Descripción | Clock Fanout Buffer/Frequency Divider | |
| Fabricantes | IDT | |
| Logotipo |  |
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Clock Fanout Buffer/Frequency Divider
8V74S4622
DATA SHEET
General Description
The 8V74S4622 is a versatile Clock Fanout Buffer/Frequency
Divider. The device supports the selection, division and distribution
of high-frequency clock signals with very low additive phase noise.
The 8V74S4622 uses SiGe technology for an optimum of high clock
frequency and low phase noise performance, combined with high
power supply noise rejection and internal isolation.
Two selectable inputs are supported for differential and single ended
clocks. Each of the two outputs can select a copy or a frequency-
divided input signal. The available frequency divisions are
divide-by-2, 4, 5 and 8. Both outputs support LVDS interfaces. For
each of the two outputs, a synchronous output enabled control is
implemented for stopping the output clock synchronously to the input
clock signal. All device configurations are through a logic pin
interface. The device is packaged in a lead-free (RoHS 6) 20-lead
VFQFN package. The extended temperature range supports
wireless infrastructure, telecommunication and networking end
equipment requirements. The device is a member of the
high-performance clock family from IDT.
Features
• Clock signal selection, frequency-division and distribution
• Two outputs individually select:
• The input signal ÷2, ÷4, ÷5 and ÷8 or
• The input signal without frequency division (input signal is
passed through)
• Two inputs to support single-ended and differential operation
• Differential input supports LVDS and LVPECL signals
• Single-ended input supports LVCMOS signals
• Two differential LVDS outputs
• Maximum Input Frequency (differential input clock): 2000MHz
• Maximum Output Frequency: 2000MHz
• Output skew: 22ps (maximum)
• Additive phase noise RMS, 125MHz, SELn = 0, 12kHz - 20MHz
integration range: 180fs (maximum)
• LVDS output rise/fall time: 260ps (maximum)
• 3.3V core and output supply voltages
• -40°C to 85°C ambient operating temperature
• Lead-free (RoHS 6) 4x4 mm2 20-lead VFQFN packaging
Pin Assignment
Block Diagram
20 19 18 17 16
SEL1 1
15 nOE0
IN 2
14 GND
VT 3
8V74S4622
13 nQ1
nIN 4
12 Q1
REFSEL 5
11 VDDO1
6 7 8 9 10
CLK
IN
nIN
VT
REFSEL
N[1:0]
SEL[1:0]
nOE0
nOE1
2x 50
0 fCLK
1
÷N
2
2
0
1 EN
0
1 EN
Q0
nQ0
Q1
nQ1
20-pin, 4mm x 4mm VFQFN Package
8V74S4622 REVISION 1 05/11/15
1
©2015 Integrated Device Technology, Inc.
1 page  
8V74S4622 DATA SHEET
Table 5C. Differential Input DC Characteristics, VDD = VDDO= 3.3V ± 5%, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
Typical
RIN
VCMR
VPP
VDIFF_IN
Differential Input
Resistance
IN, nIN
Common mode input voltage.1, 2
Input Voltage Swing2
Differential Input
Voltage Swing
IN, nIN
IN to VT, nIN to VT
50
1
0.15
0.30
IIN
Input Current
IN, nIN
NOTE: 1. VCMR is defined as the signal crosspoint.
NOTE: 2. VIL should not be less than -0.3V. VIH should not be greater than VDD.
Maximum
VDD -VPP/2
1.2
30
Units
V
V
V
mA
Table 5D. LVDS DC Characteristics, VDD = VDDO= 3.3V ± 5%, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
Minimum
VOD
VOD
VOS
VOS
Differential Output Voltage
VOD Magnitude Change
Offset Voltage
VOS Magnitude Change
247
1
Typical
Maximum
460
50
1.4
50
Units
mV
mV
V
mV
REVISION 1 05/11/15
5 CLOCK FANOUT BUFFER/FREQUENCY DIVIDER
5 Page 
8V74S4622 DATA SHEET
LVDS Driver Termination
For a general LVDS interface, the recommended value for the
termination impedance (ZT) is between 90 and 132. The actual
value should be selected to match the differential impedance (Z0) of
your transmission line. A typical point-to-point LVDS design uses a
100 parallel resistor at the receiver and a 100 differential
transmission-line environment. In order to avoid any transmission-
line reflection issues, the components should be surface mounted
and must be placed as close to the receiver as possible. IDT offers a
full line of LVDS compliant devices with two types of output
structures: current source and voltage source. The standard
termination schematic as shown in Figure 4A can be used with either
type of output structure. Figure 4B, which can also be used with both
output types, is an optional termination with center tap capacitance
to help filter common mode noise. The capacitor value should be
approximately 50pF. If using a non-standard termination, it is
recommended to contact IDT and confirm if the output structure is
current source or voltage source type. In addition, since these
outputs are LVDS compatible, the input receiver’s amplitude and
common-mode input range should be verified for compatibility with
the output.
LVDS
Driver
ZO ZT
Figure 4A. Standard LVDS Termination
LVDS
Driver
ZO ZT
Figure 4B. Optional LVDS Termination
ZT
LVDS
Receiver
ZT
2 LVDS
C ZT Receiver
2
REVISION 1 05/11/15
11 CLOCK FANOUT BUFFER/FREQUENCY DIVIDER
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet 8V74S4622.PDF ] | |
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