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PDF 9FGL02 Data sheet ( Hoja de datos )
| Número de pieza | 9FGL02 | |
| Descripción | 2-output 3.3V PCIe Clock Generator | |
| Fabricantes | IDT | |
| Logotipo |  |
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2-output 3.3V PCIe Clock Generator
9FGL02
DATASHEET
Description
The 9FGL02 devices are 3.3V members of IDT's 3.3V
Full-Featured PCIe family. The devices have 2 output enables
for clock management and support 2 different spread
spectrum levels in addition to spread off. The 9FGL02
supports PCIe Gen1-4 Common Clocked architectures (CC)
and PCIe Separate Reference no-Spread (SRnS) and
Separate Reference Independent Spread (SRIS) clocking
architectures. The 9FGL02P1 can be programmed with a
user-defined power up default SMBus configuration.
Recommended Application
PCIe Gen1-4 clock generation for Riser Cards, Storage,
Networking, JBOD, Communications, Access Points
Output Features
• 2 – 100 MHz Low-Power HCSL (LP-HCSL) DIF pairs
• 9FGL0241 default ZOUT = 100
• 9FGL0251 default ZOUT = 85
• 9FGL02P1 factory programmable defaults
• 1 - 3.3V LVCMOS REF output w/Wake-On-LAN (WOL)
support
• Easy AC-coupling to other logic families, see IDT
application note AN-891
Key Specifications
• PCIe Gen1-2-3-4 CC-compliant
• PCIe Gen2-3 SRIS-compliant
• DIF cycle-to-cycle jitter <50ps
• DIF output-to-output skew <50ps
• DIF 12k-20M phase jitter is <2ps rms when SSC is off
• REF phase jitter is <300fs rms (SSC off) and < 1.5ps RMS
(SSC on)
• ±100ppm frequency accuracy on all clocks
Block Diagram
Features/Benefits
• Direct connection to 100 (xx41) or 85 (xx51)
transmission lines; saves 8 resistors compared to standard
PCIe devices
• 112mW typical power consumption (@3.3V); eliminates
thermal concerns
• SMBus-selectable features allows optimization to customer
requirements:
• control input polarity
• control input pull up/downs
• slew rate for each output
• 33, 85 or 100Ω output impedance for each output
• spread spectrum amount
• input frequency
• 41 and 51 devices contain default configuration; SMBus
interface not required for device operation
• P1 device allows factory programming of customer-defined
input/output frequencies and SMBus power up default;
allows exact optimization to customer requirements
• OE# pins; support DIF power management
• 8MHz - 40MHz input frequency with 9FGL02P1 device
(25MHz default); flexibility
• Pin/SMBus selectable 0%, -0.25% or -0.5% spread on DIF
outputs; minimize EMI and phase jitter for each application
• DIF outputs blocked until PLL is locked; clean system
start-up
• Two selectable SMBus addresses; multiple devices can
easily share an SMBus segment
• Space saving 24-pin 4x4mm VFQFPN; minimal board
space
y
vOE(1:0)#
XIN/CLKIN_25
2
REF
603-25-150JA4I 25MHz
X2
vSADR
vSS_EN_tri
^CKPWRGD_PD#
SDATA_3.3
SCLK_3.3
Control
Logic
SSC Capable
PLL
DIF1
DIF0
Note: Resistors default to internal on 41/51 devices. P1 devices have programmable default impedances on an output-by-output basis.
9FGL02 OCTOBER 18, 2016
1 ©2016 Integrated Device Technology, Inc.
1 page  
9FGL02 DATASHEET
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the 9FGL02. These ratings, which are standard values
for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other conditions
above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating
conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the recommended
operating temperature range.
PARAMETER
SYMBOL
CONDITIONS
Supply Voltage
VDDx
Input Voltage
VIN
Input High Voltage, SMBus VIHSMB
Storage Temperature
Ts
SMBus clock and data pins
Junction Temperature
Tj
Input ESD protection ESD prot
Human Body Model
1Guaranteed by design and characterization, not 100% tested in production.
2 Operation under these conditions is neither implied nor guaranteed.
3 Not to exceed 4.6V.
MIN
-0.5
-0.5
-65
2500
Electrical Characteristics–SMBus Parameters
TA = TAMB; Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN
SMBus Input Low Voltage VILSMB
VDDSMB = 3.3V
SMBus Input High Voltage VIHSMB
VDDSMB = 3.3V
SMBus Output Low Voltage VOLSMB
@ IPULLUP
SMBus Sink Current
IPULLUP
@ VOL
Nominal Bus Voltage
VDDSMB
SCLK/SDATA Rise Time
tRSMB
(Max VIL - 0.15) to (Min VIH + 0.15)
SCLK/SDATA Fall Time
tFSMB
(Min VIH + 0.15) to (Max VIL - 0.15)
SMBus Operating
Frequency
fSMB
SMBus operating frequency
1 Guaranteed by design and characterization, not 100% tested in production.
2. The device must be powered up for the SMBus to function.
2.1
4
2.7
TYP MAX UNITS NOTES
4.6
VDD+0.5
3.9
150
125
V
V
V
°C
°C
V
1,2
1,3
1
1
1
1
TYP MAX UNITS NOTES
0.8
3.6
0.4
3.6
1000
300
V
V
V
mA
V
ns
ns
1
1
500 kHz
2
OCTOBER 18, 2016
5 2-OUTPUT 3.3V PCIE CLOCK GENERATOR
5 Page 
9FGL02 DATASHEET
SMBus Table: Output Enable Register
Byte 0
Name
Control Function
Type
0
1 Default
Bit 7
Reserved
X
Bit 6
Reserved
X
Bit 5
Reserved
X
Bit 4
Reserved
X
Bit 3
Reserved
X
Bit 2
DIF OE1
Output Enable
RW Low/Low
Pin Control
1
Bit 1
DIF OE0
Output Enable
RW Low/Low
Pin Control
1
Bit 0
Reserved
X
1. A low on these bits will overide the OE# pin and force the differential output to the state indicated by B11[1:0] (Low/Low default).
SMBus Table: SS Readback and Vhigh Control Register
Byte 1
Name
Control Function
Bit 7
SSENRB1
SS Enable Readback Bit1
Bit 6
SSENRB1
SS Enable Readback Bit0
Bit 5
SSEN_SWCNTRL
Enable SW control of SS
Bit 4
SSENSW1
SS Enable Software Ctl Bit1
Bit 3
SSENSW0
SS Enable Software Ctl Bit0
Bit 2
Bit 1
Bit 0
AMPLITUDE 1
AMPLITUDE 0
Reserved
Controls Output Amplitude
1. B1[5] must be set to a 1 for these bits to have any effect on the part.
Type
0
1
R 00' for SS_EN_tri = 0, '01' for SS_EN_tri
R = 'M', '11 for SS_EN_tri = '1'
RW
SS control locked
Values in B1[4:3]
control SS amount.
RW1
RW1
00' = SS Off, '01' = -0.25% SS,
'10' = Reserved, '11'= -0.5% SS
RW 00 = 0.6V
RW 10 = 0.75V
01= 0.68V
11 = 0.85V
Default
Latch
Latch
0
0
0
X
1
0
SMBus Table: DIF Slew Rate Control Register
Byte 2
Name
Control Function
Bit 7
Reserved
Bit 6
Reserved
Bit 5
Reserved
Bit 4
Reserved
Bit 3
Reserved
Bit 2
SLEWRATESEL DIF1
Adjust Slew Rate of DIF1
Bit 1
SLEWRATESEL DIF0
Adjust Slew Rate of DIF0
Bit 0
Reserved
Note: See "Low-Power HCSL Outputs" table for slew rates.
Type
RW
RW
0
Slow Setting
Slow Setting
1
Fast Setting
Fast Setting
Default
X
X
X
X
X
1
1
X
SMBus Table: REF Control Register
Byte 3
Name
Bit 7
Bit 6
REF
Bit 5 REF Power Down Function
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
REF OE
Control Function
Slew Rate Control
Type
RW
RW
Wake-on-Lan Enable for REF RW
REF Output Enable
Reserved
Reserved
Reserved
Reserved
RW
0
00 = Slowest
10 = Fast
REF disabled in
Power Down
Disabled
1
01 = Slow
11 = Faster
REF runs in Power
Down
Enabled
Default
0
1
0
1
X
X
X
X
Byte 4 is Reserved
OCTOBER 18, 2016
11 2-OUTPUT 3.3V PCIE CLOCK GENERATOR
11 Page | ||
| Páginas | Total 19 Páginas | |
| PDF Descargar | [ Datasheet 9FGL02.PDF ] | |
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