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ICS9FG104D 데이터시트 PDF




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부품번호 ICS9FG104D 기능
기능 Frequency Generator
제조업체 IDT
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ICS9FG104D 데이터시트, 핀배열, 회로
DATASHEET
Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
ICS9FG104D
Description
The ICS9FG104D is a Frequency Timing Generator that provides 4
differential output pairs that are compliant to the Intel CK410
specification. It also provides support for PCI-Express and SATA.
The part synthesizes several output frequencies from either a
14.31818 Mhz crystal or a 25 MHz crystal. The device can also be
driven by a reference input clock instead of a crystal. It provides
outputs with cycle-to-cycle jitter of less than 50 ps and output-to-
output skew of less than 35 ps. The ICS9FG104D also provides a
copy of the reference clock. Frequency selection can be
accomplished via strap pins or SMBus control.
Key Specifications
Features/Benefits
• Generates common frequencies from 14.318 MHz or
25 MHz
• Crystal or reference input
• 4 - 0.7V current-mode differential output pairs
• Supports Serial-ATA at 100 MHz
• Two spread spectrum modes: 0 to -0.5 downspread
and +/-0.25% centerspread
• Unused inputs may be disabled in either driven or Hi-Z
state for power management.
• Output cycle-to-cycle jitter < 50 ps
• Output to output skew < 35 ps
• +/-300 ppm frequency accuracy on output clocks
• +/-50 ppm at any frequency w/spread off
Functional Block Diagram
XIN/CLKIN
X2
2
OSC
PROGRAMMABLE
SPREAD PLL
STOP
LOGIC
4
REFOUT
DIF(3:0)
SPREAD
SEL14M_25M#
DIF_STOP#
FS(2:0)
SDATA
SCLK
CONTROL
LOGIC
IREF
IDT® Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
1
1541C—12/16/10




ICS9FG104D pdf, 반도체, 판매, 대치품
ICS9FG104D
Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
Absolute Max
Symbol
VDDxx
Parameter
3.3V Supply Voltage
Ts Storage Temperature
Tambient Ambient Operating Temp•(Commerical Grade)
Tambient Ambient Operating Temp•(Industrial Grade)
Tcase
Case Temperature
ESD prot Input ESD protection•human body model
Min
-65
0
-40
2000
Max
4.6
150
+70
+85
115
Units
V
°C
°C
°C
°C
V
Electrical Characteristics - Input/Supply/Common Output Parameters
TA = TAM BIENT; Supply Voltage VDD = 3.3 V +/-5%
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS NOTES
Input High Voltage
Input Low Voltage
Input High Current
Input Low Current
VIH
3.3 V +/-5%
2
VIL
3.3 V +/-5%
VSS - 0.3
IIH
VIN = VDD
-5
IIL1
VIN = 0 V; Inputs with no pull-
up resistors
-5
IIL2
VIN = 0 V; Inputs with pull-up -200
resistors
VDD + 0.3
0.8
5
V
V
uA
uA
uA
1
1
1
1
1
IDD3.3OP
Operating Supply Current
Input Frequency3
Pin Inductance1
Input/Output
Capacitance1
Clk Stabilization1,2
Modulation Frequency
Modulation Frequency
DIF output enable
IDD3.3STOP
Fi
Lpin
CIN
COUT
TSTABcom
TSTABind
fMOD
fMOD
tDIFOE
Full Active, CL = Full load;
f = 400 MHz
Full Active, CL = Full load;
f = 100 MHz
All outputs stopped driven
All outputs stopped Hi-Z
SEL14M_25M# = 0
SEL14M_25M# = 1
Logic Inputs
Output pin capacitance
From VDD Power-Up to 1st
clock (Commercial)
From VDD Power-Up to 1st
clock (Industrial)
SEL14M_25M# = 0
SEL14M_25M# = 1
DIF output enable after
DIF_Stop# de-assertion
125 150 mA
110 125 mA
106
48
22.5 25.00
12.886 14.31818
1.5
120
60
27.5
15.75
7
5
6
mA
mA
MHz
MHz
nH
pF
pF
1.8 ms
1.8 ms
32.541
32.467
kHz
kHz
15 ns
1
1
1
1
3
3
1
1
1
1,2
1,2
1,3,4
1,3,4
1
Input Rise and Fall times tR/tF
20% to 80% of VDD
5 ns
1Guaranteed by design, not 100% tested in production.
2See timing diagrams for timing requirements.
3 Input frequency should be measured at the REF pin and tuned to 0 PPM to meet
ppm frequency accuracy on PLL outputs.
4 These values assume 25MHz or 14.31818MHz inputs respectively. Using a higher or lower frequency
will scale these frequencies accordingly. The output frequecy selected by the FS inputs will also scale.
For example, 27MHz input with an FS selection of 100MHz will yield an output frequency of 27/25 x 100 =
108MHz.
1
IDT® Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
1541C—12/16/10
4

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ICS9FG104D 전자부품, 판매, 대치품
ICS9FG104D
Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
General SMBus serial interface information for the ICS9FG104D
How to Write:
Controller (host) sends a start bit.
• Controller (host) sends the write address DC
(H)
• ICS clock will acknowledge
• Controller (host) sends the begining byte location = N
• ICS clock will acknowledge
• Controller (host) sends the data byte count = X
• ICS clock will acknowledge
• Controller (host) starts sending Byte N through
Byte N + X -1
• ICS clock will acknowledge each byte one at a time
• Controller (host) sends a Stop bit
How to Read:
• Controller (host) will send start bit.
• Controller (host) sends the write address DC (h)
• ICS clock will acknowledge
• Controller (host) sends the begining byte
location = N
• ICS clock will acknowledge
• Controller (host) will send a separate start bit.
• Controller (host) sends the read address DD (h)
• ICS clock will acknowledge
• ICS clock will send the data byte count = X
• ICS clock sends Byte N + X -1
• ICS clock sends Byte 0 through byte X (if X(h)
was written to byte 8).
• Controller (host) will need to acknowledge each byte
• Controllor (host) will send a not acknowledge bit
• Controller (host) will send a stop bit
Index Block Write Operation
Controller (Host)
T starT bit
ICS (Slave/Receiver)
Slave Address DC(h)
WR WRite
ACK
Beginning Byte = N
ACK
Data Byte Count = X
ACK
Beginning Byte N
ACK
Byte N + X - 1
P stoP bit
ACK
IDT® Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
7
Index Block Read Operation
Controller (Host)
T starT bit
ICS (Slave/Receiver)
Slave Address DC(h)
WR WRite
ACK
Beginning Byte = N
ACK
RT Repeat starT
Slave Address DD(h)
RD ReaD
ACK
ACK
ACK
Data Byte Count = X
Beginning Byte N
N Not acknowledge
P stoP bit
Byte N + X - 1
1541C—12/16/10

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