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ICS9FG108D 데이터시트 PDF




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부품번호 ICS9FG108D 기능
기능 Frequency Generator
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ICS9FG108D 데이터시트, 핀배열, 회로
Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
DATASHEET
ICS9FG108D
Description
ICS9FG108D is a Frequency Timing Generator that provides 8
differential output pairs that are compliant to the Intel CK410
specification. It also provides support for PCI-Express, next
generation I/O, and SATA. The part synthesizes several output
frequencies from either a 14.31818 MHz crystal or a 25 MHz crystal.
The device can also be driven by a reference input clock instead of
a crystal. It provides outputs with cycle-to-cycle jitter of less than 50
ps and output-to-output skew of less than 65 ps. ICS9FG108D also
provides a copy of the reference clock. Frequency selection can be
accomplished via strap pins or SMBus control.
Key Specifications
Features/Benefits
• Generates common frequencies from 14.318 MHz or
25 MHz
• Crystal or reference input
• 8 - 0.7V current-mode differential output pairs
• Supports Serial-ATA at 100 MHz
• Two spread spectrum modes: 0 to -0.5 down spread
and +/-0.25% center spread
• Unused inputs may be disabled in either driven or Hi-Z
state for power management.
• Output cycle-to-cycle jitter < 50 ps
• Output to output skew < 65 ps
• +/-300 ppm frequency accuracy on output clocks
• +/-50 ppm at any frequency with spread off
Functional Block Diagram
XIN/CLKIN
X2
OE(7:0)
OSC
PROGRAMMABLE
SPREAD PLL
STOP
LOGIC
8
R EFOU T
DIF(7:0)
SPREAD
SEL14M_25M#
DIF_STOP#
FS(2:0)
SDATA
SCLK
CONTROL
LOGIC
IREF
IDTTM Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
1
1542E 12/16/10




ICS9FG108D pdf, 반도체, 판매, 대치품
ICS9FG108D
Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
Pin Description (continued)
PIN #
25
PIN NAME
DIF_STOP#
PIN TYPE
IN
26 vSPREAD
IN
27 ^SEL14M_25M# IN
28 vOE_3
IN
29 DIF_3#
30 DIF_3
31 VDD
32 DIF_2#
33 DIF_2
OUT
OUT
PWR
OUT
OUT
34 ^OE_2
IN
35 GND
36 VDD
PWR
PWR
37 ^OE_1
IN
38 DIF_1#
39 DIF_1
40 VDD
41 DIF_0#
42 DIF_0
OUT
OUT
PWR
OUT
OUT
43 vOE_0
IN
44 vFS1
45 vFS0
IN
IN
46 IREF
OUT
47 GNDA
PWR
48 VDDA
PWR
Note:
^ indicates internal 120K pull up
v indicates internal 120K pull down
DESCRIPTION
Active low input to stop differential output clocks.
Asynchronous, active high input to enable spread spectrum functionality. This pin has
a 120Kohm pull down resistor.
Select 14.31818 MHz or 25 Mhz input frequency. This pin has an internal 120kohm
pull up resistor.
1 = 14.31818 MHz, 0 = 25 MHz
Active high input for enabling output 3. This pin has an internal 120kohm pull down
resistor.
0 = tri-state outputs, 1= enable outputs
0.7V differential Complementary clock output
0.7V differential true clock output
Power supply, nominal 3.3V
0.7V differential Complementary clock output
0.7V differential true clock output
Active high input for enabling output 2. This pin has in internal 120kohm pull up
resistor.
0 = tri-state outputs, 1= enable outputs
Ground pin.
Power supply, nominal 3.3V
Active high input for enabling output 1. This pin has an internal 120kohm pull up
resistor.
0 = tri-state outputs, 1= enable outputs
0.7V differential Complementary clock output
0.7V differential true clock output
Power supply, nominal 3.3V
0.7V differential Complementary clock output
0.7V differential true clock output
Active high input for enabling output 0. This pin has an internal 120kohm pull down
resistor.
0 = tri-state outputs, 1= enable outputs
3.3V Frequency select latched input pin with internal 120kohm pull down resistor.
3.3V Frequency select latched input pin with internal 120kohm pull down resistor.
This pin establishes the reference current for the differential current-mode output pairs.
This pin requires a fixed precision resistor tied to ground in order to establish the
appropriate current. 475 ohms is the standard value.
Ground pin for the PLL core.
3.3V power for the PLL core.
IDTTM Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
4
1542E 12/16/10

4페이지










ICS9FG108D 전자부품, 판매, 대치품
ICS9FG108D
Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
Electrical Characteristics - DIF 0.7V Current Mode Differential Pair
TA = Tambient, Supply Voltage VDD = 3.3 V +/-5%, CL =2pF, RS=33.2,
RP=49.9, IREF = 475
PARAMETER
SYMBOL
CONDITIONS
MIN
Current Source Output
Impedance
Zo1
VO = Vx
3000
Voltage High
Voltage Low
VHigh
VLow
Statistical measurement on
single ended signal using
oscilloscope math function.
660
-150
Max Voltage
Min Voltage
Crossing Voltage (abs)
Vovs
Vuds
Vcross(abs)
Measurement on single ended
signal using absolute value.
-300
250
TYP
SPEC
MAX
UNITS NOTES
1
850
150
1150
550
mV
mV
mV
1
1
1
1
1
Crossing Voltage (var)
d-Vcross Crossing variation over all edges
140 mV
1
14.3M input, SS OFF
-300
300 ppm
Long Accuracy
ppm
14.3M input, SS ON
-300
25M input SS OFF
-50
300 ppm
50 ppm
25M input, SS ON
-300
300 ppm
400MHz nominal
2.4993
2.5008
ns
400MHz spread
2.4993
2.5133
ns
333.33MHz nominal
2.9991
3.0009
ns
333.33MHz spread
2.9991
3.016
ns
266.66MHz nominal
3.7489
3.7511
ns
266.66MHz spread
3.7489
3.77 ns
Average period
Tperiod
200MHz nominal
200MHz spread
4.9985
4.9985
5.0015
5.0266
ns
ns
166.66MHz nominal
5.9982
6.0018
ns
166.66MHz spread
5.9982
6.0320
ns
133.33MHz nominal
7.4978
7.5023
ns
133.33MHz spread
7.4978
5.4000
ns
100.00MHz nominal
9.9970
10.0030 ns
100.00MHz spread
9.9970
10.0533 ns
400MHz nominal/spread
2.4143
ns
333.33MHz nominal/spread 2.9141
ns
266.66MHz nominal/spread 3.6639
ns
Absolute min period
Tabsmin
200MHz nominal/spread
4.8735
ns
166.66MHz nominal/spread 5.8732
ns
133.33MHz nominal/spread 7.3728
ns
100.00MHz nominal/spread 9.8720
ns
Rise Time
tr
VOL = 0.175V, VOH = 0.525V
175
700 ps
Fall Time
tf
VOH = 0.525V VOL = 0.175V
175
700 ps
Rise Time Variation
d-tr
125 ps
Fall Time Variation
d-tf
125 ps
Duty Cycle
dt3
Measured Differentially
45
55 %
Skew, output to output
tsk3COM
tsk3IND
TA = Commercial, VT=50%
TA = Industrial, VT=50%
50 ps
65 ps
Jitter, Cycle to cycle
tjcyc-cyc
Measurement from differential
wavefrom
50 ps
1Guaranteed by design and characterization, not 100% tested in production.
2 All Long Term Accuracy and Clock Period specifications are guaranteed assuming that REFOUT is at
14.31818MHz or 25 MHz
3 Figures are for down spread.
4 This figure is the peak-to-peak phase jitter as defined by PCI-SIG for a PCI Express reference clock. Please visit
http://www.pcisig.com for additional details
5 +/- 50 ppm at any frequency with spread off
IDTTM Frequency Generator for CPU, QPI, FBD, PCIe Gen 2 & SATA
1,2,5
1,2,5
1,2,5
1,2,5
2
2,3
2
2,3
2
2,3
2
2,3
2
2,3
2
2,3
2
2,3
1,2
1,2
1,2
1,2
1,2
1,2
1,2
1
1
1
1
1
1
1
1
1542E 12/16/10
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