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9FG1901H 데이터시트 PDF




IDT에서 제조한 전자 부품 9FG1901H은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


 

PDF 형식의 9FG1901H 자료 제공

부품번호 9FG1901H 기능
기능 Frequency Generator
제조업체 IDT
로고 IDT 로고


9FG1901H 데이터시트 를 다운로드하여 반도체의 전기적 특성과 매개변수에 대해 알아보세요.




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9FG1901H 데이터시트, 핀배열, 회로
Frequency Gearing Clock for CPU, PCIe Gen1 & FBD
DATASHEET
9FG1901H
Description
Features/Benefits
The 9FG1901H follows the Intel DB1900G Differential Buffer
Specification. This buffer provides 19 output clocks for CPU Host
Bus, PCI-Express, or Fully Buffered DIMM applications. The outputs
are configured with two groups. Both groups, DIF_(16:0) and
DIF_(18:17) can be equal to or have a gear ratio to the input clock.
A differential CPU clock from a CK410B+ main clock generator,
such as the ICS932S421, drives the ICS9FG1901. The 9FG1901H
can provide outputs up to 400MHz.
Power up default is all outputs in 1:1 mode
DIF_(16:0) can be “gear-shifted” from the input CPU Host
Clock
DIF_(18:17) can be “gear-shifted” from the input CPU Host
Clock
Spread spectrum compatible
Supports output clock frequencies up to 400 MHz
8 Selectable SMBus addresses
SMBus address determines PLL or Bypass mode
Key Specifications
• VDDA controlled power down mode
• DIF output cycle-to-cycle jitter < 50ps
• DIF output-to-output skew across all outputs in 1:1 mode < 150ps
Functional Block Diagram
OE_17_18#
OE(16:5)#, 13
OE_01234#
CLK_IN
CLK_IN#
HIGH_BW#
FS_A_410
SMB_A0
SMB_A1
SMB_A2_PLLBYP#
SMBDAT
SMBCLK
SPREAD
COMPATIBLE
PLL
SPREAD
COMPATIBLE
PLL
CONTROL
LOGIC
GEAR
SHIFT
LOGIC
STOP
LOGIC
2
DIF(18:17)
GEAR
SHIFT
LOGIC
STOP
LOGIC
17
DIF(16:0)
IREF
IDTTM Frequency Gearing Clock for CPU, PCIe Gen1 & FBD
1
1386A - 02/02/10




9FG1901H pdf, 반도체, 판매, 대치품
9FG1901H
Frequency Gearing Clock for CPU, PCIe Gen1 & FBD
Pin Description (continued)
PIN #
PIN NAME
PIN TYPE
37 OE9#
IN
38 DIF_9
39 DIF_9#
OUT
OUT
40 OE10#
IN
41 DIF_10
42 DIF_10#
OUT
OUT
43 OE11#
IN
44 DIF_11
45 DIF_11#
46 GND
47 VDD
OUT
OUT
PWR
PWR
48 OE12#
IN
49 DIF_12
50 DIF_12#
OUT
OUT
51 OE13#
IN
52 DIF_13
53 DIF_13#
OUT
OUT
54 OE14#
IN
55 DIF_14
56 DIF_14#
OUT
OUT
57 OE15#
IN
58 DIF_15
59 DIF_15#
OUT
OUT
60 OE16#
IN
61 DIF_16
62 DIF_16#
63 VDD
64 GND
65 DIF_17
66 DIF_17#
67 DIF_18
68 DIF_18#
OUT
OUT
PWR
PWR
OUT
OUT
OUT
OUT
69 OE17_18#
IN
70 CLK_IN
71 CLK_IN#
IN
IN
72 SMB_A2_PLLBYP#
IN
DESCRIPTION
Active low input for enabling DIF pair 9.
1 = tri-state outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential complement clock output
Active low input for enabling DIF pair 10.
1 = tri-state outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential complement clock output
Active low input for enabling DIF pair 11.
1 = tri-state outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential complement clock output
Ground pin.
Power supply, nominal 3.3V
Active low input for enabling DIF pair 12.
1 = tri-state outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential complement clock output
Active low input for enabling DIF pair 13.
1 = tri-state outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential complement clock output
Active low input for enabling DIF pair 14.
1 = tri-state outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential complement clock output
Active low input for enabling DIF pair 15.
1 = tri-state outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential complement clock output
Active low input for enabling DIF pair 16.
1 = tri-state outputs, 0 = enable outputs
0.7V differential true clock output
0.7V differential complement clock output
Power supply, nominal 3.3V
Ground pin.
0.7V differential true clock output
0.7V differential complement clock output
0.7V differential true clock output
0.7V differential complement clock output
Active low input for enabling DIF pairs 17 and 18.
1 = tri-state outputs, 0 = enable outputs
True Input for differential reference clock.
Complement Input for differential reference clock.
SMBus address bit 2. When Low, the part operates as a fanout buffer with the
PLL bypassed. When High, the part operates as a zero-delay buffer (ZDB) with
the PLL operating.
0 = fanout mode (PLL bypassed), 1 = ZDB mode (PLL used)
IDTTM Frequency Gearing Clock for CPU, PCIe Gen1 & FBD
1386A - 02/02/10
4

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9FG1901H 전자부품, 판매, 대치품
9FG1901H
Frequency Gearing Clock for CPU, PCIe Gen1 & FBD
General SMBus serial interface information for the 9FG1901H
How to Write:
Controller (host) sends a start bit.
• Controller (host) sends the write address D0 (h)
• ICS clock will acknowledge
• Controller (host) sends the begining byte location = N
• ICS clock will acknowledge
• Controller (host) sends the data byte count = X
• ICS clock will acknowledge
• Controller (host) starts sending Byte N through
Byte N + X -1
• ICS clock will acknowledge each byte one at a time
• Controller (host) sends a Stop bit
How to Read:
• Controller (host) will send start bit.
• Controller (host) sends the write address D0 (h)
• ICS clock will acknowledge
• Controller (host) sends the begining byte
location = N
• ICS clock will acknowledge
• Controller (host) will send a separate start bit.
• Controller (host) sends the read address D1 (h)
• ICS clock will acknowledge
• ICS clock will send the data byte count = X
• ICS clock sends Byte N + X -1
• ICS clock sends Byte 0 through byte X (if X(h)
was written to byte 8).
• Controller (host) will need to acknowledge each byte
• Controllor (host) will send a not acknowledge bit
• Controller (host) will send a stop bit
Index Block Write Operation
Controller (Host)
T starT bit
ICS (Slave/Receiver)
Slave Address D0(h)*
WR WRite
ACK
Beginning Byte = N
ACK
Data Byte Count = X
ACK
Beginning Byte N
ACK
Byte N + X - 1
P stoP bit
ACK
Index Block Read Operation
Controller (Host)
ICS (Slave/Receiver)
T starT bit
Slave Address D0(h)*
WR WRite
ACK
Beginning Byte = N
ACK
RT Repeat starT
Slave Address D1(h)*
RD ReaD
ACK
ACK
ACK
Data Byte Count = X
Beginning Byte N
N Not acknowledge
P stoP bit
* Note: See SMBus Address Mapping (page 6), for programming SMBus Read/Write Address
IDTTM Frequency Gearing Clock for CPU, PCIe Gen1 & FBD
7
Byte N + X - 1
1386A - 02/02/10

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9FG1901H

Frequency Generator

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