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9FGL06 데이터시트 PDF




IDT에서 제조한 전자 부품 9FGL06은 전자 산업 및 응용 분야에서
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부품번호 9FGL06 기능
기능 6-output 3.3V PCIe Clock Generator
제조업체 IDT
로고 IDT 로고


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9FGL06 데이터시트, 핀배열, 회로
6-output 3.3V PCIe Clock Generator
9FGL06
DATASHEET
Description
The 9FGL06 devices are 3.3V members of IDT's 3.3V
Full-Featured PCIe family. The devices have 6 output enables
for clock management and support 2 different spread
spectrum levels in addition to spread off. The 9FGL06
supports PCIe Gen1-4 Common Clocked architectures (CC)
and PCIe Separate Reference no-Spread (SRnS) and
Separate Reference Independent Spread (SRIS) clocking
architectures. The 9FGL06P1 can be programmed with a
user-defined power up default SMBus configuration.
Recommended Application
PCIe Gen1-4 clock generation for Riser Cards, Storage,
Networking, JBOD, Communications, Access Points
Output Features
6 – 100 MHz Low-Power HCSL (LP-HCSL) DIF pairs
9FGL0641 default ZOUT = 100
9FGL0651 default ZOUT = 85
9FGL06P1 factory programmable defaults
1 - 3.3V LVCMOS REF output w/Wake-On-LAN (WOL)
support
Easy AC-coupling to other logic families, see IDT
application note AN-891
Key Specifications
PCIe Gen1-2-3-4 CC-compliant
PCIe Gen2-3 SRIS-compliant
DIF cycle-to-cycle jitter <50ps
DIF output-to-output skew <50ps
DIF 12k-20M phase jitter is <2ps rms when SSC is off
REF phase jitter is <300fs rms, SSC off, and <1.5ps rms,
SSC is On
±100ppm frequency accuracy on all clocks
Block Diagram
Features/Benefits
Direct connection to 100(xx41) or 85(xx51)
transmission lines; saves 24 resistors compared to
standard PCIe devices
172mW typical power consumption (@3.3V); eliminates
thermal concerns
SMBus-selectable features allows optimization to customer
requirements:
control input polarity
control input pull up/downs
slew rate for each output
differential output amplitude
33, 85 or 100output impedance for each output
spread spectrum amount
41 and 51 devices contain default configuration; SMBus
interface not required for device operation
P1 device allows factory programming of customer-defined
SMBus power up default; allows exact optimization to
customer requirements
8MHz - 40MHz input frequency with 9FGL08P1 device
(25MHz default); flexibility
OE# pins; support DIF power management
Pin/SMBus selectable 0%, -0.25% or -0.5% spread on DIF
outputs; minimize EMI and phase jitter for each application
DIF outputs blocked until PLL is locked; clean system
start-up
Two selectable SMBus addresses; multiple devices can
easily share an SMBus segment
Space saving 40-pin 5x5mm VFQFPN; minimal board
space
vOE(5:0)#
XIN/CLKIN_25
603-25-150JA4I 25MHz
X2
6
vSADR
vSS_EN_tri
^CKPWRGD_PD#
SDATA_3.3
SCLK_3.3
Control
Logic
SSC Capable
PLL
REF
DIF5
DIF4
DIF3
DIF2
DIF1
DIF0
Note: Resistors default to internal on 41/51 devices. P1 devices have programmable default impedances on an output-by-output basis.
9FGL06 OCTOBER 19, 2016
1 ©2016 Integrated Device Technology, Inc.




9FGL06 pdf, 반도체, 판매, 대치품
9FGL06 DATASHEET
Test Loads
Low-Power Differential Output Test Load
Rs
Rs
5 inches
Zo=100ohm
2pF 2pF
Note: The device can drive transmission line lengths greater
than those specified by the PCIe SIG
REF Output Test Load
Terminations
Device
9FGL0641
9FGL0651
9FGL06P1
9FGL0641
9FGL0651
9FGL06P1
Zo ()
100
100
100
85
85
85
Rs ()
None needed
7.5
Prog.
N/A
None needed
Prog.
Zo = 50 ohms
33
5pF
REF Output
Alternate Terminations
The 9FGL family can easily drive LVPECL, LVDS, and CML logic. See “AN-891 Driving LVPECL, LVDS, and CML Logic with
IDT's "Universal" Low-Power HCSL Outputs” for details.
6-OUTPUT 3.3V PCIE CLOCK GENERATOR
4
OCTOBER 19, 2016

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9FGL06 전자부품, 판매, 대치품
9FGL06 DATASHEET
Electrical Characteristics–DIF Low-Power HCSL Outputs
TA = TAMB; Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
Slew rate
Crossing Voltage (abs)
Crossing Voltage (var)
SYMBOL
Trf
Vcross_abs
Δ-Vcross
CONDITIONS
Scope averaging on, fast setting
Scope averaging, slow setting
Scope averaging off
Scope averaging off
MIN TYP MAX UNITS NOTES
2 2.7 4 V/ns 2,3
1 1.9 3 V/ns 2,3
250 409 550 mV 1,4,5
14 140 mV 1,4,9
Avg. Clock Period Accuracy TPERIOD_AVG
-100 0.0 +2600 ppm 2,10,13
Absolute Period
Jitter, Cycle to cycle
Voltage High
Voltage Low
TPERIOD_ABS
tjcyc-cyc
VHIGH
VLOW
Includes jitter and Spread Spectrum Modulation 9.94906
Statistical measurement on single-ended signal
using oscilloscope math function. (Scope
averaging on)
660
-150
10.0 10.1011
16 50
761 850
-7 150
ns
ps
mV
2,6
2
1
1
Absolute Max Voltage
Vmax
Absolute Min Voltage
Vmin
Duty Cycle
Slew rate matching
tDC
ΔTrf
Skew, Output to Output
tsk3
1 Measured from single-ended waveform.
2 Measured from differential waveform.
Measurement on single ended signal using
absolute value. (Scope averaging off)
Averaging on, VT = 50%
-300
819
-46
1150
mV
1,7,15
1,8,15
45 49 55 %
2
6 20 % 1,14
35 50 ps
2
3 Measured from -150 mV to +150 mV on the differential waveform (derived from REFCLK+ minus REFCLK-). The signal must be monotonic
through the measurement region for rise and fall time. The 300 mV measurement window is centered on the differential zero crossing.
4 Measured at crossing point where the instantaneous voltage value of the rising edge of REFCLK+ equals the falling edge of REFCLK-.
5 Refers to the total variation from the lowest crossing point to the highest, regardless of which edge is crossing. Refers to all crossing
points for this measurement.
6 Defines as the absolute minimum or maximum instantaneous period. This includes cycle to cycle jitter, relative PPM tolerance, and spread
spectrum modulation.
7 Defined as the maximum instantaneous voltage including overshoot.
8 Defined as the minimum instantaneous voltage including undershoot.
9 Defined as the total variation of all crossing voltages of Rising REFCLK+ and Falling REFCLK-. This is the maximum allowed variance in
VCROSS for any particular system.
10 Refer to Section 4.3.7.1.1 of the PCI Express Base Specification, Revision 3.0 for information regarding PPM considerations.
11 System board compliance measurements must use the test load. REFCLK+ and REFCLK- are to be measured at the load capacitors CL.
Single ended probes must be used for measurements requiring single ended measurements. Either single ended probes with math or
differential probe can be used for differential measurements. Test load CL = 2 pF.
12 TSTABLE is the time the differential clock must maintain a minimum ±150 mV differential voltage after rising/falling edges before it is
allowed to droop back into the VRB ±100 mV differential range.
13 PPM refers to parts per million and is a DC absolute period accuracy specification. 1 PPM is 1/1,000,000th of 100.000000 MHz exactly or
100 Hz. For 300 PPM, then we have an error budget of 100 Hz/PPM * 300 PPM = 30 kHz. The period is to be measured with a frequency
counter with measurement window set to 100 ms or greater. The ±300 PPM applies to systems that do not employ Spread Spectrum
Clocking, or that use common clock source. For systems employing Spread Spectrum Clocking, there is an additional 2,500 PPM nominal
shift in maximum period resulting from the 0.5% down spread resulting in a maximum average period specification of +2,800 PPM.
14 Matching applies to rising edge rate for REFCLK+ and falling edge rate for REFCLK-. It is measured using a ±75 mV window centered on
the median cross point where REFCLK+ rising meets REFCLK- falling. The median cross point is used to calculate the voltage thresholds
the oscilloscope is to use for the edge rate calculations. The Rise Edge Rate of REFCLK+ should be compared to the Fall Edge Rate of
REFCLK-; the maximum allowed difference should not exceed 20% of the slowest edge rate.
15 At default SMBus amplitude settings.
OCTOBER 19, 2016
7 6-OUTPUT 3.3V PCIE CLOCK GENERATOR

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