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9FGU0831 데이터시트 PDF




IDT에서 제조한 전자 부품 9FGU0831은 전자 산업 및 응용 분야에서
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부품번호 9FGU0831 기능
기능 8-O/P 1.5V PCIe Gen 1-2-3 Clock Generator
제조업체 IDT
로고 IDT 로고


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9FGU0831 데이터시트, 핀배열, 회로
8-O/P 1.5V PCIe Gen 1-2-3 Clock Generator 9FGU0831
DATASHEET
General Description
The 9FGU0831 is a member of IDT's 1.5V Ultra-Low-Power
PCIe clock family. The device has 8 output enables for clock
management, 2 different spread spectrum levels in addition to
spread off and 2 selectable SMBus addresses.
Recommended Application
1.5V PCIe Gen1-2-3 Clock Generator
Output Features
8 - 100MHz Low-Power (LP) HCSL DIF pairs
1 - 1.5V LVCMOS REF output w/Wake-On-LAN (WOL)
support
Key Specification
DIF cycle-to-cycle jitter <50ps
DIF output-to-output skew < 60ps
DIF phase jitter is PCIe Gen1-2-3 compliant
REF phase jitter is < 3.0ps RMS
Functional Block Diagram
Features/Benefits
LP-HCSL outputs; save 16 resistors compared to standard
PCIe devices
50mW typical power consumption; reduced thermal
concerns
Outputs can optionally be supplied from any voltage
between 1.05 and 1.5V; maximum power savings
OE# pins; support DIF power management
Programmable Slew rate for each output; allows tuning for
various line length
Programmable output amplitude; allows tuning for various
application environments
DIF outputs blocked until PLL is locked; clean system
start-up
Selectable 0%, -0.25% or -0.5% spread on DIF outputs;
reduces EM
External 25MHz crystal; supports tight ppm with 0 ppm
synthesis error
Configuration can be accomplished with strapping pins;
SMBus interface not required for device control
Selectable SMBus addresses; multiple devices can easily
share an SMBus segment
3.3V tolerant SMBus interface works with legacy controllers
Space saving 48-pin 6x6 mm VFQFPN; minimal board
space
vOE(7:0)#
XIN/CLKIN_25
X2
OSC
vSADR
vSS_EN_tri
^CKPWRGD_PD#
SDATA_3.3
SCLK_3.3
CONTROL
LOGIC
SS Capable PLL
REF1.5
DIF7
DIF6
DIF5
DIF4
DIF3
DIF2
DIF1
DIF0
9FGU0831 OCTOBER 18, 2016
1 ©2016 Integrated Device Technology, Inc.




9FGU0831 pdf, 반도체, 판매, 대치품
9FGU0831 DATASHEET
Pin Descriptions (cont.)
PIN # PIN NAME
40 GND
41 DIF6
42 DIF6#
TYPE
GND
OUT
OUT
43 vOE6#
IN
44 DIF7
45 DIF7#
OUT
OUT
46 vOE7#
IN
47 VDDIO
PWR
48 ^CKPWRGD_PD#
IN
DESCRIPTION
Ground pin.
Differential true clock output
Differential Complementary clock output
Active low input for enabling DIF pair 6. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
Differential true clock output
Differential Complementary clock output
Active low input for enabling DIF pair 7. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
Power supply for differential outputs
Input notifies device to sample latched inputs and start up on first high
assertion. Low enters Power Down Mode, subsequent high assertions exit
Power Down Mode. This pin has internal pull-up resistor.
8-O/P 1.5V PCIE GEN 1-2-3 CLOCK GENERATOR
4
OCTOBER 18, 2016

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9FGU0831 전자부품, 판매, 대치품
9FGU0831 DATASHEET
Electrical Characteristics – Input/Supply/Common Parameters - Normal Operating
Conditions
TA = TAMB; Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS NOTES
Supply Voltage
VDDxx
Supply voltage for core, analog and single-ended
LVCMOS outputs
Output Supply Voltage
VDDIO Supply voltage for differential Low Power Outputs
Ambient Operating
Temperature
TAMB
Comercial range
Industrial range
Input High Voltage
Input Mid Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Input Current
Input Frequency
Pin Inductance
Capacitance
Clk Stabilization
VIH
VIM
VIL
VIH
VIL
IIN
IINP
Fin
Lpin
CIN
COUT
TSTAB
Single-ended inputs, except SMBus
Single-ended tri-level inputs ('_tri' suffix)
Single-ended inputs, except SMBus
Single-ended outputs, except SMBus. IOH = -2mA
Single-ended outputs, except SMBus. IOL = -2mA
Single-ended inputs, VIN = GND, VIN = VDD
Single-ended inputs
VIN = 0 V; Inputs with internal pull-up resistors
VIN = VDD; Inputs with internal pull-down resistors
XTAL, or X1 input
Logic Inputs, except DIF_IN
Output pin capacitance
From VDD Power-Up and after input clock
stabilization or de-assertion of PD# to 1st clock
SS Modulation Frequency
OE# Latency
fMOD
tLATOE#
Triangular Modulation
DIF start after OE# assertion
DIF stop after OE# deassertion
Tdrive_PD#
tDRVPD
DIF output enable after
PD# de-assertion
Tfall
Trise
SMBus Input Low Voltage
SMBus Input High Voltage
SMBus Output Low Voltage
SMBus Sink Current
Nominal Bus Voltage
SCLK/SDATA Rise Time
SCLK/SDATA Fall Time
SMBus Operating
Frequency
tF
tR
VILSMB
VIHSMB
VOLSMB
IPULLUP
VDDSMB
tRSMB
tFSMB
fMAXSMB
Fall time of single-ended control inputs
Rise time of single-ended control inputs
VDDSMB = 3.3V, see note 4 for VDDSMB < 3.3V
@ IPULLUP
@ VOL
(Max VIL - 0.15) to (Min VIH + 0.15)
(Min VIH + 0.15) to (Max VIL - 0.15)
Maximum SMBus operating frequency
1 Guaranteed by design and characterization, not 100% tested in production.
2 Control input must be monotonic from 20% to 80% of input swing.
3 Time from deassertion until outputs are >200 mV
4 For VDDSMB < 3.3V, VIHSMB >= 0.8xVDDSMB
1.425 1.5 1.575
0.9975
0
-40
0.75 VDD
0.4 VDD
-0.3
VDD-0.45
-5
1.05-1.5
25
25
0.5 VDD
1.575
70
85
VDD + 0.3
0.6 VDD
0.25 VDD
0.45
5
V
V
°C
°C
V
V
V
V
V
uA
-200
200 uA
23 25 27 MHz
7 nH
1.5 5 pF
6 pF
1.8 ms
30 31.6 33 kHz
1 3 clocks
2.1
4
1.425
300
5
5
0.6
3.3
0.4
3.3
1000
300
400
us
ns
ns
V
V
V
mA
V
ns
ns
kHz
1
1
1
1,2
1
1,3
1,3
2
2
4
1
1
1
OCTOBER 18, 2016
7 8-O/P 1.5V PCIE GEN 1-2-3 CLOCK GENERATOR

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9FGU0831

8-O/P 1.5V PCIe Gen 1-2-3 Clock Generator

IDT
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