PDF 9FGV0831 Data sheet ( Hoja de datos )

Número de pieza	9FGV0831
Descripción	8-O/P 1.8V PCIe Gen 1/2/3 Clock Generator
Fabricantes	IDT
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No Preview Available ! 8-O/P 1.8V PCIe Gen 1/2/3 Clock Generator 9FGV0831 DATASHEET Description The 9FGV0831 is a member of IDT's SOC-Friendly 1.8V Very-Low-Power PCIe clock family. The device has 8 output enables for clock management, 2 different spread spectrum levels in addition to spread off and 2 selectable SMBus addresses. Recommended Application 1.8V PCIe Gen1/2/3 clock generator Output Features • 8 - 100MHz Low-Power (LP) HCSL DIF pair • 1 - 1.8V LVCMOS REF output w/Wake-On-LAN (WOL) support Key Specifications • DIF cycle-to-cycle jitter <50ps • DIF output-to-output skew <50ps • DIF phase jitter is PCIe Gen1-2-3 compliant • REF phase jitter is < 1.5ps RMS Block Diagram Features/Benefits • LP-HCSL outputs; save 16 resistors compared to standard PCIe devices • 62mW typical power consumption; reduced thermal concerns • Outputs can optionally be supplied from any voltage between 1.05 and 1.8V; maximum power savings • OE# pins; support DIF power management • Programmable Slew rate for each output; allows tuning for various line lengths • Programmable output amplitude; allows tuning for various application environments • DIF outputs blocked until PLL is locked; clean system start-up • Selectable 0%, -0.25% or -0.5% spread on DIF outputs; reduces EMI • External 25MHz crystal; supports tight ppm with 0 ppm synthesis error • Configuration can be accomplished with strapping pins; SMBus interface not required for device control • 3.3V tolerant SMBus interface works with legacy controllers • Selectable SMBus addresses; multiple devices can easily share an SMBus segment • Space saving 48-pin 6x6 mm VFQFPN; minimal board space vOE(7:0)# XIN/CLKIN_25 X2 OSC vSADR vSS_EN_tri ^CKPWRGD_PD# SDATA_3.3 SCLK_3.3 CONTROL LOGIC SS Capable PLL REF1.8 DIF7 DIF6 DIF5 DIF4 DIF3 DIF2 DIF1 DIF0 9FGV0831 OCTOBER 18, 2016 1 ©2016 Integrated Device Technology, Inc. 1 page Test Loads Low-Power Differential Output Test Load Rs Rs 5 inches Zo=100ohms 2pF 2pF 9FGV0831 DATASHEET Alternate Differential Output Terminations Rs Zo Units 33 27 100 85 Ohms REF Output Test Load Zo = 50 ohms 33 5pF REF Output Alternate Terminations Driving LVDS Rs Rs Cc Cc 3.3 Volts R7a R7b Zo R8a R8b Driving LVDS inputs Value Receiver has Receiver does not Component termination have termination Note R7a, R7b 10K ohm 140 ohm R8a, R8b 5.6K ohm 75 ohm Cc 0.1 uF 0.1 uF Vcm 1.2 volts 1.2 volts OCTOBER 18, 2016 5 LVDS CLK Input 8-O/P 1.8V PCIE GEN 1/2/3 CLOCK GENERATOR 5 Page 9FGV0831 DATASHEET SMBus Table: Output Enable Register 1 Byte 0 Name Control Function Type 0 Bit 7 DIF OE7 Output Enable RW Low/Low Bit 6 DIF OE6 Output Enable RW Low/Low Bit 5 DIF OE5 Output Enable RW Low/Low Bit 4 DIF OE4 Output Enable RW Low/Low Bit 3 DIF OE3 Output Enable RW Low/Low Bit 2 DIF OE2 Output Enable RW Low/Low Bit 1 DIF OE1 Output Enable RW Low/Low Bit 0 DIF OE0 Output Enable RW Low/Low 1. A low on these bits will overide the OE# pin and force the differential output Low/Low 1 Enabled Enabled Enabled Enabled Enabled Enabled Enabled Enabled Default 1 1 1 1 1 1 1 1 SMBus Table: SS Readback and Control Register Byte 1 Bit 7 Bit 6 Name SSENRB1 SSENRB1 Control Function SS Enable Readback Bit1 SS Enable Readback Bit0 Bit 5 SSEN_SWCNTRL Enable SW control of SS Bit 4 SSENSW1 SS Enable Software Ctl Bit1 Bit 3 SSENSW0 SS Enable Software Ctl Bit0 Bit 2 Reserved Bit 1 Bit 0 AMPLITUDE 1 AMPLITUDE 0 Controls Output Amplitude 1. B1[5] must be set to a 1 for these bits to have any effect on the part. Type 0 1 Default R 00' for SS_EN_tri = 0, '01' for SS_EN_tri Latch R = 'M', '11 for SS_EN_tri = '1' Latch RW Values in B1[7:6] Values in B1[4:3] control SS amount control SS amount. 0 RW1 RW1 RW RW 00' = SS Off, '01' = -0.25% SS, '10' = Reserved, '11'= -0.5% SS 00 = 0.6V 10= 0.8V 01 = 0.7V 11 = 0.9V 0 0 1 1 0 SMBus Table: DIF Slew Rate Control Register Byte 2 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Name SLEWRATESEL DIF7 SLEWRATESEL DIF6 SLEWRATESEL DIF5 SLEWRATESEL DIF4 SLEWRATESEL DIF3 SLEWRATESEL DIF2 SLEWRATESEL DIF1 SLEWRATESEL DIF0 Control Function Adjust Slew Rate of DIF7 Adjust Slew Rate of DIF6 Adjust Slew Rate of DIF5 Adjust Slew Rate of DIF4 Adjust Slew Rate of DIF3 Adjust Slew Rate of DIF2 Adjust Slew Rate of DIF1 Adjust Slew Rate of DIF0 Type RW RW RW RW RW RW RW RW 0 Slow Setting Slow Setting Slow Setting Slow Setting Slow Setting Slow Setting Slow Setting Slow Setting 1 Fast Setting Fast Setting Fast Setting Fast Setting Fast Setting Fast Setting Fast Setting Fast Setting Default 1 1 1 1 1 1 1 1 SMBus Table: Nominal Vhigh Amplitude Control/ REF Control Register Byte 3 Bit 7 Bit 6 Bit 5 Name REF REF Power Down Function Control Function Slew Rate Control Wake-on-Lan Enable for REF Type 0 1 RW 00 = Slowest 01 = Slow RW 10 = Fast 11 = Faster RW REF does not run in REF runs in Power Power Down Down Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 REF OE REF Output Enable Reserved Reserved Reserved Reserved RW Low Enabled Default 0 1 0 1 1 1 1 1 Byte 4 is Reserved OCTOBER 18, 2016 11 8-O/P 1.8V PCIE GEN 1/2/3 CLOCK GENERATOR 11 Page

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