PDF ST7781R Data sheet ( Hoja de datos )

Número de pieza	ST7781R
Descripción	240RGB x 320 dot 262K Color / Single-Chip TFT Controller/Driver
Fabricantes	Sitronix Technology
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ST7781R 240RGB x 320 dot 262K Color with Frame Memory Single-Chip TFT Controller/Driver Datasheet Version 1.0 2010/09 Sitronix Technology Corp. reserves the right to change the contents in this document without prior notice. 1 page ST7781R LIST OF FIGURES Figure 1 Parallel Interface Timing Characteristics (8080-Series MCU Interface) ........................................... 47 Figure 2 Rising and Falling Timing for I/O Signal ............................................................................................ 48 Figure 3 Write-to-Read and Read-to-Write Timing.......................................................................................... 48 Figure 4 SPI Interface Timing Characteristics ................................................................................................. 49 Figure 5 RGB Interface Timing Characteristics ............................................................................................... 50 Figure 6 8080-Series WRX Protocol ............................................................................................................... 53 Figure 7 8080-Series Parallel Bus Protocol, Write to Register or Display RAM ............................................. 53 Figure 8 8080-18 bits Interface Data Format (Command Write/DRAM Write)................................................ 54 Figure 9 8080-16 bits Interface Data Format (Command Write/Display RAM Write) ..................................... 55 Figure 10 8080-9 bits Interface Data Format (Command Write/Display RAM Write) ..................................... 56 Figure 11 8080-8 bits interface data format (command write/Display RAM write) .......................................... 58 Figure 12 8080-Series RDX Protocol .............................................................................................................. 59 Figure 13 8080-series parallel bus protocol, read data from register or display RAM .................................... 59 Figure 14 8080-18 bits Interface Data Format (Command Read/Display RAM Read) ................................... 60 Figure 15 8080-16 bits Interface Data Format (Command Read/Display RAM Read) ................................... 61 Figure 16 8080-9 bits Interface Data Format (Command Read/Display RAM Read) ..................................... 62 Figure 17 8080-8 bits Interface Data Format (Command Read/Display RAM Read) ..................................... 63 Figure 18 DRAM Address Map Table.............................................................................................................. 64 Figure 19 RGB Interface Data Format............................................................................................................. 65 Figure 20 DRAM Access Area by RGB Interface............................................................................................ 66 Figure 21 Timing Chart of Signals in 18-/16-bit RGB Interface Mode............................................................. 67 Figure 22 Timing chart of signals in 6-bit RGB interface mode....................................................................... 68 Figure 23 Example of update the still and moving picture............................................................................... 70 Figure 24 Example of 6-bit RGB interface data format ................................................................................... 71 Figure 25 6-bit Transfer Synchronization ........................................................................................................ 72 Figure 26 Example of 16-Bit RGB Interface and Data Format........................................................................ 73 Figure 27 Example of 18-bit RGB Interface and Data Format ........................................................................ 74 Figure 28 Internal clock operation/RGB interface mode switching ................................................................. 75 Figure 29 DRAM access between system interface and RGB interface......................................................... 76 Figure 30 Data Format of SPI Interface........................................................................................................... 78 Figure 31 Data transmission through serial peripheral interface (SPI) ........................................................... 79 Figure 32 Data transmission through serial peripheral interface (SPI, TRI=”1” and DFM=”1 or 0”) ............... 80 Figure 33 Data transmission through VSYNC interface .................................................................................. 81 Figure 34 Operation through VSYNC Interface............................................................................................... 81 Figure 35 Timing Diagram of VSYNC Interface .............................................................................................. 82 Figure 36 Operation for Leading Mode of VSYNC Interface ........................................................................... 83 Figure 37 Operation for Lagging Mode of VSYNC Interface ........................................................................... 83 Version 1.0 Page 5 of 155 2010/09 5 Page 3 PAD ARRANGEMENT 3.1.. Output Bump Dimension Au bump height Au bump size 12µm 16µmx90µm Gate : G1~G320 Source : S1~S720 50µmx80µm Input Pads : Pad1 to Pad243 Bump View DUMMY DUMMY DUMMY VPP VPP TPO0 IM0/ID IM1 IM2 IM3 DUMMY TPO1 TPO2 TPO3 TPO4 TPO5 TPO6 TPO7 RESET RESET VSYNC HSYNC DOTCLK ENABLE DB17 DB16 DB15 DB14 DB13 DUMMY DB12 DB11 DB10 DB9 DB8 DUMMY DUMMY DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 DUMMY SDO SDI RDX WRX(SCL) DCX(RS) CSX DUMMY OSC FMARK DUMMY TPI3 TPI2 TPI1 TPI0 DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY VDDI VDDI VDDI VDDI VDDI VDDI VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC DUMMY DGND DGND DGND DGND DGND DGND DGND DGND AGND AGND AGND AGND AGND AGND AGND AGND AGND AGND AGND AGND DUMMY DUMMY DUMMY VCOM VCOM VCOM VCOM VCOM VCOM VCOM AVCL AVCL AVCL AVCL AVCL AVCL GVCL GVCL GVCL GVCL GVDD GVDD GVDD DUMMY DUMMY DUMMY VCL VCL VCL VCL VCL AVDD AVDD AVDD AVDD AVDD AVDD DUMMY DUMMY DUMMY VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD VDD DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY VGL VGL VGL VGL VGL VGL VGL VGL VGL VGL AGND AGND AGND VGH VGH VGH VGH VGH VGH DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY DUMMY Version 1.0 Page 11 of 155 ST7781R DUMMY G319 G317 G315 G313 G311 G309 G307 G305 G303 G 17 G 15 G 13 G 11 G9 G7 G5 G3 G1 DUMMY DUMMY S1 S2 S3 S4 S5 S6 S7 S8 S9 X S353 S354 S355 S356 S357 S358 S359 S360 DUMMY Y DUMMY S361 S362 S363 S364 S365 S366 S367 S368 S369 S712 S713 S714 S715 S716 S717 S718 S719 S720 DUMMY DUMMY G2 G4 G6 G8 G10 G12 G14 G16 G18 G304 G306 G308 G310 G312 G314 G316 G318 G320 DUMMY 2010/09 11 Page

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