|
|
PDF 9DB1233 Data sheet ( Hoja de datos )
| Número de pieza | 9DB1233 | |
| Descripción | Twelve Output Differential Buffer | |
| Fabricantes | IDT | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de 9DB1233 (archivo pdf) en la parte inferior de esta página. Total 15 Páginas | ||
|
No Preview Available !
Twelve Output Differential Buffer for PCIe Gen3
DATASHEET
9DB1233
Recommended Application
12 output PCIe Gen3 zero-delay/fanout buffer
General Description
The 9DB1233 zero-delay buffer supports PCIe Gen3
requirements, while being backwards compatible to PCIe Gen2
and Gen1. The 9DB1233 is driven by a differential SRC output
pair from an IDT 932S421 or 932SQ420 or equivalent main
clock generator. It attenuates jitter on the input clock and has a
selectable PLL bandwidth to maximize performance in systems
with or without Spread-Spectrum clocking.
Output Features
• 12 - 0.7V current mode differential HCSL output pairs
Features/Benefits
• 3 Selectable SMBus Addresses/Mulitple devices can share
the same SMBus Segment
• 12 OE# pins/Hardware control of each output
• PLL or bypass mode/PLL can dejitter incoming clock
• Selectable PLL bandwidth/minimizes jitter peaking in
downstream PLL's
• Spread Spectrum Compatible/tracks spreading input clock
for low EMI
• SMBus Interface/unused outputs can be disabled
• Supports undriven differential outputs in Power Down mode
for power management
Key Specifications
• Output cycle-cycle jitter < 50ps.
• Output-to-output skew < 50 ps
• PCIe Gen3 phase jitter < 1.0ps RMS
• Pin compatible with DB1200 Yellow Cover Device
Functional Block Diagram
12
OE_(11:0)#
DIF_IN
DIF_IN#
SPREAD
COMPATIBLE
PLL
M
U
X
12
DIF(11:0))
HIGH_BW#
BYPASS#/PLL
VTTPWRGD#/PD
ADR_SEL
SMBDAT
SMBCLK
CONTROL
LOGIC
IREF
IDT® Twelve Output Differential Buffer for PCIe Gen3
1
1675B—11/08/10
1 page  
9DB1233
Twelve Output Differential Buffer for PCIe Gen3
Electrical Characteristics - Absolute Maximum Ratings
PARAMETER
SYMBOL
CONDITIONS
3.3V Core Supply Voltage VDDA
3.3V Logic Supply Voltage VDD
Input Low Voltage
VIL
Input High Voltage
VIH
Except for SMBus interface
Input High Voltage
VIHSMB
SMBus clock and data pins
Storage Temperature
Ts
Junction Temperature
Tj
Input ESD protection ESD prot
Human Body Model
1Guaranteed by design and characterization, not 100% tested in production.
2 Operation under these conditions is neither implied nor guaranteed.
MIN
GND-0.5
-65
2000
TYP
MAX UNITS NOTES
4.6 V 1,2
4.6 V 1,2
V1
VDD+0.5V
5.5V
V
V
1
1
150 °C 1
125 °C 1
V1
Electrical Characteristics - Input/Supply/Common Parameters
TA = TCOM; Supply Voltage VDD = 3.3 V +/-5%
PARAMETER
SYMBOL
CONDITIONS
Ambient Operating
Temperature
Input High Voltage
TCOM
VIH
Commmercial range
Single-ended inputs, except SMBus, low
threshold and tri-level inputs
Input Low Voltage
VIL
Single-ended inputs, except SMBus, low
threshold and tri-level inputs
IIN Single-ended inputs, VIN = GND, VIN = VDD
MIN TYP
0
2
GND - 0.3
-5
Input Current
Single-ended inputs
IINP
VIN = 0 V; Inputs with internal pull-up resistors
-200
VIN = VDD; Inputs with internal pull-down resistors
Input Frequency
Pin Inductance
Capacitance
Clk Stabilization
Fibyp
Fipll
Lpin
CIN
CINDIF_IN
VDD = 3.3 V, Bypass mode
VDD = 3.3 V, 100MHz PLL mode
Logic Inputs, except DIF_IN
DIF_IN differential clock inputs
10
90 100.00
1.5
1.5
COUT
Output pin capacitance
TSTAB
From VDD Power-Up and after input clock
stabilization or de-assertion of PD# to 1st clock
MAX UNITS NOTES
70
VDD + 0.3
°C
V
1
1
0.8 V 1
5 uA 1
200 uA 1
166 MHz 2
110 MHz 2
7 nH 1
5 pF 1
5 pF 1,4
6 pF 1
1.8 ms 1,2
Input SS Modulation
Frequency
fMODIN
Allowable Frequency
(Triangular Modulation)
30
33 kHz 1
OE# Latency
tLATOE#
DIF start after OE# assertion
DIF stop after OE# deassertion
Tdrive_PD#
tDRVPD
DIF output enable after
PD# de-assertion
Tfall tF Fall time of control inputs
Trise tR Rise time of control inputs
SMBus Input Low Voltage VILSMB
SMBus Input High Voltage VIHSMB
SMBus Output Low Voltage VOLSMB
@ IPULLUP
SMBus Sink Current
IPULLUP
@ VOL
Nominal Bus Voltage
VDDSMB
3V to 5V +/- 10%
SCLK/SDATA Rise Time
tRSMB
(Max VIL - 0.15) to (Min VIH + 0.15)
SCLK/SDATA Fall Time
SMBus Operating
Frequency
tFSMB
fMAXSMB
(Min VIH + 0.15) to (Max VIL - 0.15)
Maximum SMBus operating frequency
1Guaranteed by design and characterization, not 100% tested in production.
2Control input must be monotonic from 20% to 80% of input swing.
3Time from deassertion until outputs are >200 mV
4DIF_IN input
5The differential input clock must be running for the SMBus to be active
IDT® Twelve Output Differential Buffer for PCIe Gen3
4
2.1
4
2.7
12 cycles 1,3
300
5
5
0.8
VDDSMB
0.4
5.5
1000
300
100
us
ns
ns
V
V
V
mA
V
ns
ns
kHz
1,3
1,2
1,2
1
1
1
1
1
1
1
1,5
1675B—11/08/10
5
5 Page 
9DB1233
Twelve Output Differential Buffer for PCIe Gen3
General SMBus serial interface information for the 9DB1233
How to Write:
• Controller (host) sends a start bit.
• Controller (host) sends the write address DC (h)
• IDT clock will acknowledge
• Controller (host) sends the begining byte location = N
• IDT clock will acknowledge
• Controller (host) sends the data byte count = X
• IDT clock will acknowledge
• Controller (host) starts sending Byte N through
Byte N + X -1
• IDT clock will acknowledge each byte one at a time
• Controller (host) sends a Stop bit
Index Block Write Operation
Controller (Host)
T starT bit
IDT (Slave/Receiver)
Slave Address DC(h)
WR WRite
ACK
Beginning Byte = N
ACK
Data Byte Count = X
ACK
Beginning Byte N
ACK
Byte N + X - 1
P stoP bit
ACK
How to Read:
• Controller (host) will send start bit.
• Controller (host) sends the write address DC (h)
• IDT clock will acknowledge
• Controller (host) sends the begining byte
location = N
• IDT clock will acknowledge
• Controller (host) will send a separate start bit.
• Controller (host) sends the read address DD (h)
• IDT clock will acknowledge
• IDT clock will send the data byte count = X
• IDT clock sends Byte N + X -1
• IDT clock sends Byte 0 through byte X (if X(h)
was written to byte 8).
• Controller (host) will need to acknowledge each byte
• Controllor (host) will send a not acknowledge bit
• Controller (host) will send a stop bit
Index Block Read Operation
Controller (Host)
T starT bit
IDT (Slave/Receiver)
Slave Address DC(h)
WR WRite
ACK
Beginning Byte = N
ACK
RT Repeat starT
Slave Address DD(h)
RD ReaD
ACK
ACK
ACK
Data Byte Count = X
Beginning Byte N
Note: Addresses show assumes pin 29 is low.
IDT® Twelve Output Differential Buffer for PCIe Gen3
N Not acknowledge
P stoP bit
Byte N + X - 1
1675B—11/08/10
11
11 Page | ||
| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet 9DB1233.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| 9DB1233 | Twelve Output Differential Buffer | IDT |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |