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9DB233 데이터시트 PDF




IDT에서 제조한 전자 부품 9DB233은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


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부품번호 9DB233 기능
기능 Two Output Differential Buffer
제조업체 IDT
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9DB233 데이터시트, 핀배열, 회로
DATASHEET
Two Output Differential Buffer for PCIe Gen3
9DB233
Recommended Application:
2 output PCIe Gen3 zero-delay/fanout buffer
General Description:
The 9DB233 zero-delay buffer supports PCIe Gen3
requirements, while being backwards compatible to PCIe
Gen2 and Gen1. The 9DB233 is driven by a differential SRC
output pair from an IDT 932S421 or 932SQ420 or equivalent
main clock generator. It attenuates jitter on the input clock
and has a selectable PLL bandwidth to maximize
performance in systems with or without Spread-Spectrum
clocking. An SMBus interface allows control of the PLL
bandwidth and bypass options, while 2 clock request (OE#)
pins make the 9DB233 suitable for Express Card
applications.
Features/Benefits:
• OE# pins/Suitable for Express Card applications
• PLL or bypass mode/PLL can dejitter incoming clock
• Selectable PLL bandwidth/minimizes jitter peaking in
downstream PLL's
• Spread Spectrum Compatible/tracks spreading input
clock for low EMI
• SMBus Interface/unused outputs can be disabled
Output Features:
• 2 - 0.7V current mode differential output pairs (HCSL)
Key Specifications:
• Cycle-to-cycle jitter < 50 ps
• Output-to-output skew < 50 ps
• PCIe Gen3 phase jitter < 1.0ps RMS
Block Diagram
OE0#
OE1#
SRC_IN
SRC_IN#
PLL_BW
SMBDAT
SMBCLK
SPREAD
COMPATIBLE
PLL
CONTROL
LOGIC
DIF_0
DIF_1
IREF
IDT® Two Output Differential Buffer for PCIe Gen3
1
1667C—04/20/11




9DB233 pdf, 반도체, 판매, 대치품
9DB233
Two Output Differential Buffer for PCIe Gen3
Datasheet
Electrical Characteristics - Absolute Maximum Ratings
PARAMETER
SYMBOL
CONDITIONS
3.3V Core Supply Voltage VDDA
3.3V Logic Supply Voltage VDD
Input Low Voltage
VIL
Input High Voltage
VIH
Except for SMBus interface
Input High Voltage
VIHSMB
SMBus clock and data pins
Storage Temperature
Ts
Junction Temperature
Tj
Input ESD protection ESD prot
Human Body Model
1Guaranteed by design and characterization, not 100% tested in production.
2 Operation under these conditions is neither implied nor guaranteed.
MIN
GND-0.5
-65
2000
TYP
MAX
4.6
4.6
VDD+0.5V
5.5V
150
125
UNITS
V
V
V
V
V
°C
°C
V
NOTES
1,2
1,2
1
1
1
1
1
1
Electrical Characteristics - Input/Supply/Common Parameters
TA = TCOM or TIND; Supply Voltage VDD = 3.3 V +/-5%
PARAMETER
SYMBOL
CONDITIONS
MIN TYP
Ambient Operating
Temperature
Input High Voltage
Input Low Voltage
TCOM
TIND
VIH
VIL
IIN
Commmercial range
Industrial range
Single-ended inputs, except SMBus, low
threshold and tri-level inputs
Single-ended inputs, except SMBus, low
threshold and tri-level inputs
Single-ended inputs, VIN = GND, VIN = VDD
0
-40
2
GND - 0.3
-5
Input Current
Single-ended inputs
IINP
VIN = 0 V; Inputs with internal pull-up resistors
-200
VIN = VDD; Inputs with internal pull-down resistors
Input Frequency
Pin Inductance
Capacitance
Clk Stabilization
Fibyp
Fipll
Lpin
CIN
CINDIF_IN
VDD = 3.3 V, Bypass mode
VDD = 3.3 V, 100MHz PLL mode
Logic Inputs, except DIF_IN
DIF_IN differential clock inputs
10
33 100.00
1.5
1.5
COUT
Output pin capacitance
TSTAB
From VDD Power-Up and after input clock
stabilization or de-assertion of PD# to 1st clock
MAX
70
85
UNITS NOTES
°C 1
°C 1
VDD + 0.3 V
1
0.8 V 1
5 uA 1
200 uA 1
110 MHz 2
110 MHz 2
7 nH 1
5 pF 1
2.7 pF 1,4
6 pF 1
1.8 ms 1,2
Input SS Modulation
Frequency
fMODIN
Allowable Frequency
(Triangular Modulation)
30
33 kHz 1
OE# Latency
tLATOE#
DIF start after OE# assertion
DIF stop after OE# deassertion
Tdrive_PD#
tDRVPD
DIF output enable after
PD# de-assertion
Tfall tF Fall time of control inputs
Trise tR Rise time of control inputs
SMBus Input Low Voltage VILSMB
SMBus Input High Voltage VIHSMB
SMBus Output Low Voltage VOLSMB
@ IPULLUP
SMBus Sink Current
IPULLUP
@ VOL
Nominal Bus Voltage
VDDSMB
3V to 5V +/- 10%
SCLK/SDATA Rise Time
tRSMB
(Max VIL - 0.15) to (Min VIH + 0.15)
SCLK/SDATA Fall Time
SMBus Operating
Frequency
tFSMB
fMAXSMB
(Min VIH + 0.15) to (Max VIL - 0.15)
Maximum SMBus operating frequency
1Guaranteed by design and characterization, not 100% tested in production.
2Control input must be monotonic from 20% to 80% of input swing.
3Time from deassertion until outputs are >200 mV
4DIF_IN input
5The differential input clock must be running for the SMBus to be active
IDT® Two Output Differential Buffer for PCIe Gen3
1
2.1
4
2.7
3 cycles 1,3
300
5
5
0.8
VDDSMB
0.4
5.5
1000
300
100
us
ns
ns
V
V
V
mA
V
ns
ns
kHz
1,3
1,2
1,2
1
1
1
1
1
1
1
1,5
1667C—04/20/11
4

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9DB233 전자부품, 판매, 대치품
9DB233
Two Output Differential Buffer for PCIe Gen3
Datasheet
SRC Reference Clock
Common Recommendations for Differential Routing
Dimension or Value
L1 length, route as non-coupled 50ohm trace
0.5 max
L2 length, route as non-coupled 50ohm trace
0.2 max
L3 length, route as non-coupled 50ohm trace
0.2 max
Rs 33
Rt 49.9
Unit Figure
inch 1
inch 1
inch 1
ohm 1
ohm 1
Down Device Differential Routing
L4 length, route as coupled microstrip 100ohm differential trace 2 min to 16 max
L4 length, route as coupled stripline 100ohm differential trace 1.8 min to 14.4 max
inch 1
inch 1
Differential Routing to PCI Express Connector
L4 length, route as coupled microstrip 100ohm differential trace 0.25 to 14 max
L4 length, route as coupled stripline 100ohm differential trace 0.225 min to 12.6 max
inch
inch
2
2
Figure 1: Down Device Routing
L1 L2
Rs
HCSL Output Buffer
L1'
L2'
Rs
Rt
L4
L4'
Rt
L3' L3
PCI Express
Down Device
REF_CLK Input
Figure 2: PCI Express Connector Routing
L1 L2
Rs
HCSL Output Buffer
L1'
L2'
Rs
Rt
L4
L4'
Rt PCI Express
Add-in Board
REF_CLK Input
L3' L3
IDT® Two Output Differential Buffer for PCIe Gen3
7
1667C—04/20/11

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9DB233

Two Output Differential Buffer

IDT
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