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9DB433 데이터시트 PDF




IDT에서 제조한 전자 부품 9DB433은 전자 산업 및 응용 분야에서
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부품번호 9DB433 기능
기능 FOUR OUTPUT DIFFERENTIAL BUFFER
제조업체 IDT
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9DB433 데이터시트, 핀배열, 회로
FOUR OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1,2,3
DATASHEET
9DB433
General Description
The 9DB433 zero-delay buffer supports PCIe Gen3
requirements, while being backwards compatible to PCIe
Gen2 and Gen1. The 9DB433 is driven by a differential
SRC output pair from an IDT 932S421 or 932SQ420 or
equivalent main clock generator.
Recommended Application
4 output PCIe Gen1,2,3 zero-delay/fanout buffer
Key Specifications
Output cycle-cycle jitter <50ps
Output to Output skew <50ps
Phase jitter: PCIe Gen3 <1.0ps rms
Functional Block Diagram
OE(6,1)#
2
Features/Benefits
3 Selectable SMBus Addresses; Mulitple devices can
share the same SMBus Segment
OE# pins; Suitable for Express Card applications
PLL or bypass mode; PLL can dejitter incoming clock
Selectable PLL bandwidth; minimizes jitter peaking in
downstream PLL's
Spread Spectrum Compatible; tracks spreading input
clock for low EMI
SMBus Interface; unused outputs can be disabled
Supports undriven differential outputs in Power Down
mode for power management
Output Features
4 - 0.7V current-mode differential HCSL output pairs
Supports zero delay buffer mode and fanout mode
Selectable bandwidth
50-110 MHz operation in PLL mode
5-166 MHz operation in Bypass mode
SRC_IN
SRC_IN#
SPREAD
COMPATIBLE
PLL
M
U
X
STOP
LOGIC
4
DIF(6,5,2,1)
PD#
BYP#_LOBW_HIBW
SMBDAT
SMBCLK
CONTROL
LOGIC
IREF
IDT® FOUR OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1,2,3
1
9DB433
REV G 08/25/15




9DB433 pdf, 반도체, 판매, 대치품
9DB433
FOUR OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1,2,3
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the 9DB433. These ratings, which are standard
values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other
conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over
the recommended operating temperature range.
PARAMETER
SYMBOL
CONDITIONS
3.3V Core Supply Voltage VDDA/R
3.3V Logic Supply Voltage VDD
Input Low Voltage
VIL
Input High Voltage
VIH
Except for SMBus interface
Input High Voltage
VIHSMB
SMBus clock and data pins
Storage Temperature
Ts
Junction Temperature
Tj
Input ESD protection ESD prot
Human Body Model
1Guaranteed by design and characterization, not 100% tested in production.
2 Operation under these conditions is neither implied nor guaranteed.
MIN
GND-0.5
-65
2000
TYP
MAX
4.6
4.6
VDD+0.5V
5.5V
150
125
UNITS
V
V
V
V
V
°C
°C
V
NOTES
1,2
1,2
1
1
1
1
1
1
Electrical Characteristics–DIF 0.7V Current Mode Differential Outputs
TA = TCOM or TIND; Supply Voltage VDD = 3.3 V +/-5%
PARAMETER
SYMBOL
CONDITIONS
Slew rate
Trf
Scope averaging on
Slew rate matching Trf Slew rate matching, Scope averaging on
MIN TYP MAX UNITS NOTES
1 2 4 V/ns 1, 2, 3
20 % 1, 2, 4
Voltage High
Voltage Low
VHigh
VLow
Statistical measurement on single-ended signal 660 800 850
using oscilloscope math function. (Scope
mV
averaging on)
-150 14 150
1
1
Max Voltage
Min Voltage
Vmax
Vmin
Measurement on single ended signal using
absolute value. (Scope averaging off)
806 1150 mV
-300 -1
1
1
Vswing
Vswing
Scope averaging off (Differential)
300 1552
mV 1, 2
Crossing Voltage (abs)
Crossing Voltage (var)
Vcross_abs
-Vcross
Scope averaging off
Scope averaging off
250 375 550 mV 1, 5
18 140 mV 1, 6
1Guaranteed by design and characterization, not 100% tested in production. IREF = VDD/(3xRR). For RR = 475(1%), IREF = 2.32mA.
IOH = 6 x IREF and VOH = 0.7V @ ZO=50(100differential impedance).
2 Measured from differential waveform
3 Slew rate is measured through the Vswing voltage range centered around differential 0V. This results in a +/-150mV window around
differential 0V.
4 Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/-75mV window centered on
the average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the
oscilloscope is to use for the edge rate calculations.
5 Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising
edge (i.e. Clock rising and Clock# falling).
6 The total variation of all Vcross measurements in any particular system. Note that this is a subset of V_cross_min/max (V_cross
absolute) allowed. The intent is to limit Vcross induced modulation by setting V_cross_delta to be smaller than V_cross absolute.
IDT® FOUR OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1,2,3
4
9DB433
REV G 08/25/15

4페이지










9DB433 전자부품, 판매, 대치품
9DB433
FOUR OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1,2,3
Electrical Characteristics–PCIe Phase Jitter Parameters
TA = TCOM or TIND; Supply Voltage VDD = 3.3 V +/-5%
PARAMETER
SYMBOL
CONDITIONS
tjphPCIeG1
PCIe Gen 1
PCIe Gen 2 Lo Band
Phase Jitter, PLL Mode
tjphPCIeG2
10kHz < f < 1.5MHz
PCIe Gen 2 High Band
1.5MHz < f < Nyquist (50MHz)
tjphPCIeG3
PCIe Gen 3
(PLL BW of 2-4MHz, CDR = 10MHz)
MIN TYP MAX
30 86
1.0 3
2.2 3.1
0.5 1
tjphPCIeG1
PCIe Gen 1
15
Additive Phase Jitter,
Bypass Mode
tjphPCIeG2
PCIe Gen 2 Lo Band
10kHz < f < 1.5MHz
PCIe Gen 2 High Band
1.5MHz < f < Nyquist (50MHz)
0.1
0.2
tjphPCIeG3
PCIe Gen 3
(PLL BW of 2-4MHz, CDR = 10MHz)
0.0
1 Applies to all outputs.
2 See http://www.pcisig.com for complete specs
3 Sample size of at least 100K cycles. This figures extrapolates to 108ps pk-pk @ 1M cycles for a BER of 1-12.
4 Subject to final radification by PCI SIG.
0.1
0.3
0.1
UNITS
ps (p-p)
ps
(rms)
ps
(rms)
ps
(rms)
Notes
1,2,3
1,2
1,2
1,2,4
ps (p-p) 1,2,3
ps
(rms)
ps
(rms)
ps
(rms)
1,2
1,2
1,2,4
Clock Periods–Differential Outputs Tracking Spread Spectrum
Measurement
Window
Symbol
1 Clock
Lg-
1us 0.1s 0.1s 0.1s 1us
-SSC -ppm error 0ppm + ppm error +SSC
1 Clock
Lg+
Definition
DIF 100
Absolute Short-term Long-Term
Long-Term Short-term
Period Average Average
Period
Average Average
Period
Minimum
Absolute
Period
9.949
Minimum
Absolute
Period
9.999
Minimum
Absolute
Period
10.024
Nominal
10.025
Maximum Maximum Maximum
10.026
10.051
Units Notes
10.101 ns 1,2,3
Clock Periods–Differential Outputs not Tracking Spread Spectrum
Measurement
Window
Symbol
1 Clock
Lg-
1us 0.1s 0.1s 0.1s 1us
-SSC -ppm error 0ppm + ppm error +SSC
1 Clock
Lg+
Absolute Short-term Long-Term
Period Average Average
Period
Definition
Minimum Minimum Minimum
Absolute Absolute Absolute Nominal
Period Period Period
DIF 100M 9.949
9.999
10.000
1Guaranteed by design and characterization, not 100% tested in production.
Long-Term Short-term
Average Average
Period
Maximum Maximum Maximum
Units Notes
10.001
10.051 ns 1,2,3
2 All Long Term Accuracy specifications are guaranteed with the assumption that the input clock complies with CK410B+ accuracy
requirements. The buffer itself does not contribute to ppm error.
3 Driven by PCIe output of main clock, PLL Mode or Bypass mode
IDT® FOUR OUTPUT DIFFERENTIAL BUFFER FOR PCIE GEN1,2,3
7
9DB433
REV G 08/25/15

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FOUR OUTPUT DIFFERENTIAL BUFFER

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