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9DBU0431 데이터시트 PDF




IDT에서 제조한 전자 부품 9DBU0431은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


 

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부품번호 9DBU0431 기능
기능 4 O/P 1.5V PCIe Gen1-2-3 ZDB/FOB
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9DBU0431 데이터시트, 핀배열, 회로
4 O/P 1.5V PCIe Gen1-2-3 ZDB/FOB
9DBU0431
DATASHEET
Description
The 9DBU0431 is a member of IDT's 1.5V Ultra-Low-Power
(ULP) PCIe family. The device has 4 output enables for clock
management, and 3 selectable SMBus addresses.
Recommended Application
1.5V PCIe Gen1-2-3 Zero-Delay/Fan-out Buffer (ZDB/FOB)
Output Features
4 – 1-167MHz Low-Power (LP) HCSL DIF pairs
Key Specifications
DIF cycle-to-cycle jitter <50ps
DIF output-to-output skew <50ps
DIF phase jitter is PCIe Gen1-2-3 compliant
DIF bypass mode additive phase jitter is <300fs rms for
PCIe Gen3
DIF bypass mode additive phase jitter <350fs rms for
12k-20MHz
Block Diagram
Features/Benefits
LP-HCSL outputs; save 8 resistors compared to standard
HCSL outputs
45mW typical power consumption in PLL mode; eliminates
thermal concerns
Spread Spectrum (SS) compatible; allows SS for EMI
reduction
OE# pins; support DIF power management
HCSL-compatible differential input; can be driven by
common clock sources
SMBus-selectable features; optimize signal integrity to
application
slew rate for each output
differential output amplitude
Pin/software selectable PLL bandwidth and PLL Bypass;
optimize PLL to application
Outputs blocked until PLL is locked; clean system start-up
Device contains default configuration; SMBus interface not
required for device control
3.3V tolerant SMBus interface works with legacy controllers
Three selectable SMBus addresses; multiple devices can
easily share an SMBus segment
Space saving 32-pin 5x5mm VFQFPN; minimal board
space
vOE(3:0)#
4
CLK_IN
CLK_IN#
vSADR
^vHIBW_BYPM_LOBW#
^CKPWRGD_PD#
SDATA_3.3
SCLK_3.3
SS-
Compatible
PLL
CONTROL
LOGIC
DIF3
DIF2
DIF1
DIF0
9DBU0431 REVISION C 04/22/15 1 ©2014 Integrated Device Technology, Inc.




9DBU0431 pdf, 반도체, 판매, 대치품
9DBU0431 DATASHEET
Test Loads
Low-Power Differential Output Test Load
5 inches
Rs
Zo=100
Rs
Note: The device can drive transmission line lengths greater
than those allowed by the PCIe SIG.
2pF 2pF
Alternate Differential Output Terminations
Rs Zo Units
33 100 Ohms
27 85
Driving LVDS
Driving LVDS
Rs
Device
Rs
Cc
Cc
3.3V
R7a
L4
R8a
R7b
R8b
LVDS Clock
input
Driving LVDS inputs
Value
Receiver has Receiver does not
Component
termination have termination Note
R7a, R7b
10K ohm
140 ohm
R8a, R8b
5.6K ohm
75 ohm
Cc
0.1 uF
0.1 uF
Vcm
1.2 volts
1.2 volts
4 O/P 1.5V PCIE GEN1-2-3 ZDB/FOB
4
REVISION C 04/22/15

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9DBU0431 전자부품, 판매, 대치품
9DBU0431 DATASHEET
Electrical Characteristics–DIF Low-Power HCSL Outputs
TA = TAMB; Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS NOTES
Slew rate
Slew rate matching
dV/dt
dV/dt
ΔdV/dt
Scope averaging on, fast setting
Scope averaging on, slow setting
Slew rate matching, Scope averaging on
1.4 2.2 3.5 V/ns 1,2,3
0.9 1.7 2.5 V/ns 1,2,3
2.7 20 % 1,2,4
Voltage High
Voltage Low
VHIGH
VLOW
Statistical measurement on single-ended signal 630 735 850
using oscilloscope math function. (Scope
mV
averaging on)
-150 -16 150
7
7
Max Voltage
Min Voltage
Vmax
Vmin
Measurement on single ended signal using
absolute value. (Scope averaging off)
779 1150 mV
-300 -45
7
7
Vswing
Vswing
Scope averaging off
300 1503
mV 1,2
Crossing Voltage (abs) Vcross_abs
Scope averaging off
250 405 550 mV 1,5
Crossing Voltage (var)
Δ-Vcross
Scope averaging off
12 140 mV 1,6
1Guaranteed by design and characterization, not 100% tested in production.
2 Measured from differential waveform
3 Slew rate is measured through the Vswing voltage range centered around differential 0V. This results in a +/-150mV window around
differential 0V.
4 Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/-75mV window centered on
the average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the
oscilloscope is to use for the edge rate calculations.
5 Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising
edge (i.e. Clock rising and Clock# falling).
6 The total variation of all Vcross measurements in any particular system. Note that this is a subset of Vcross_min/max (Vcross
absolute) allowed. The intent is to limit Vcross induced modulation by setting Δ-Vcross to be smaller than Vcross absolute.
7 At default SMBus settings.
Electrical Characteristics–Current Consumption
TA = TAMB; Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN
IDDR VDDR @100MHz
Operating Supply Current
IDDDIG
VDDIG, All outputs @100MHz
IDDAO VDDA+VDDO, PLL Mode, All outputs @100MHz
IDDRPD
VDDR, CKPWRGD_PD# = 0
Powerdown Current
IDDDIGPD
IDDAOPD
VDDDIG, CKPWRGD_PD# = 0
VDDA+VDDO, CKPWRGD_PD# = 0
1 Guaranteed by design and characterization, not 100% tested in production.
2 Input clock stopped.
3 In bypass mode, the PLL is off and IDDAO is ~50% of this value.
TYP
4
0.125
24
0.1
0.1
0.5
MAX
6
0.25
30
0.3
0.2
1
UNITS
mA
mA
mA
mA
mA
mA
NOTES
1
1
1
1,2,3
1,2
1,2
REVISION C 04/22/15
7 4 O/P 1.5V PCIE GEN1-2-3 ZDB/FOB

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9DBU0431

4 O/P 1.5V PCIe Gen1-2-3 ZDB/FOB

IDT
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