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PDF 9DBV0541 Data sheet ( Hoja de datos )
| Número de pieza | 9DBV0541 | |
| Descripción | 5 O/P 1.8V PCIe Gen1-2-3 Fan-out Buffer | |
| Fabricantes | IDT | |
| Logotipo |  |
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5 O/P 1.8V PCIe Gen1-2-3 Fan-out Buffer
w/Zo=100ohms
9DBV0541
DATASHEET
Description
The 9DBV0541 is a member of IDT's 1.8V Very-Low-Power
(VLP) PCIe family. It has integrated terminations for direct
connection to 100ohm transmission lines. The device has 5
output enables for clock management, and 3 selectable
SMBus addresses.
Recommended Application
1.8V PCIe Gen1-2-3 Fan-out Buffer (FOB)
Output Features
• 5 – 1-200MHz Low-Power (LP) HCSL DIF pairs
w/Zo=100
Key Specifications
• DIF additive cycle-to-cycle jitter <5ps
• DIF output-to-output skew < 50ps
• DIF additive phase jitter is <100fs rms for PCIe Gen3
• DIF additive phase jitter <300fs rms for SGMII
Features/Benefits
• Integrated terminations; save 36 resistors compared to
standard HCSL outputs
• 50mW typical power consumption; minimal power
consumption
• OE# pins; support DIF power management
• HCSL compatible differential input; can be driven by
common clock sources
• Programmable Slew rate for each output; allows tuning for
various line lengths
• Programmable output amplitude; allows tuning for various
application environments
• 1MHz to 200MHz operating frequency
• 3.3V tolerant SMBus interface works with legacy controllers
• Selectable SMBus addresses; multiple devices can easily
share an SMBus segment
• Device contains default configuration; SMBus interface not
required for device operation
• Space saving 32-pin 5x5mm VFQFPN; minimal board
space
Block Diagram
vOE(4:0)#
CLK_IN
CLK_IN#
vSADR
^CKPWRGD_PD#
SDATA_3.3
SCLK_3.3
5
CONTROL
LOGIC
DIF4
DIF3
DIF2
DIF1
DIF0
9DBV0541 REVISION B 08/28/14 1 ©2014 Integrated Device Technology, Inc.
1 page  
9DBV0541 DATASHEET
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the 9DBV0541. These ratings, which are standard
values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other
conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over the
recommended operating temperature range.
PARAMETER
SYMBOL
CONDITIONS
Supply Voltage
VDDx
Applies to all VDD's
Input Voltage
VIN
Input High Voltage, SMBus VIHSMB
Storage Temperature
Ts
SMBus clock and data pins
Junction Temperature
Tj
Input ESD protection ESD prot
Human Body Model
1Guaranteed by design and characterization, not 100% tested in production.
2 Operation under these conditions is neither implied nor guaranteed.
3 Not to exceed 2.5V.
MIN
-0.5
-0.5
-65
2000
TYP
MAX
2.5
VDD+0.5
3.6
150
125
UNITS NOTES
V 1,2
V 1,3
V1
°C 1
°C 1
V1
Electrical Characteristics–Clock Input Parameters
TA = TCOM or TIND; Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN TYP
Input High Voltage - DIF_IN VIHDIF
Input Low Voltage - DIF_IN
Input Common Mode
Voltage - DIF_IN
VILDIF
VCOM
Differential inputs
(single-ended measurement)
Differential inputs
(single-ended measurement)
Common Mode Input Voltage
300 750
VSS - 300
200
0
Input Amplitude - DIF_IN
Input Slew Rate - DIF_IN
VSWING
dv/dt
Peak to Peak value (VIHDIF - VILDIF)
Measured differentially
300
0.35
Input Leakage Current
IIN
VIN = VDD , VIN = GND
Input Duty Cycle dtin Measurement from differential wavefrom
Input Jitter - Cycle to Cycle JDIFIn
Differential Measurement
1 Guaranteed by design and characterization, not 100% tested in production.
2 Slew rate measured through +/-75mV window centered around differential zero
-5
45
0
MAX
1150
UNITS NOTES
mV 1
300 mV 1
725
1450
8
5
55
150
mV
mV
V/ns
uA
%
ps
1
1
1,2
1
1
REVISION B 08/28/14
5 5 O/P 1.8V PCIE GEN1-2-3 FAN-OUT BUFFER W/ZO=100OHMS
5 Page 
9DBV0541 DATASHEET
SMBus Table: Output Enable Register 1
Byte 0
Name
Control Function
Type
0
Bit 7
Reserved
Bit 6
DIF OE3
Output Enable
RW Low/Low
Bit 5
DIF OE2
Output Enable
RW Low/Low
Bit 4
Reserved
Bit 3
DIF OE1
Output Enable
RW Low/Low
Bit 2
Reserved
Bit 1
DIF OE0
Output Enable
RW Low/Low
Bit 0
Reserved
1. A low on these bits will overide the OE# pin and force the differential output Low/Low
SMBus Table: PLL Operating Mode and Output Amplitude Control Register
Byte 1
Name
Control Function
Type
0
Bit 7
Reserved
Bit 6
Reserved
Bit 5
DIF OE4
Output Enable
RW Low/Low
Bit 4
Reserved
Bit 3
Reserved
Bit 2
Reserved
Bit 1
Bit 0
AMPLITUDE 1
AMPLITUDE 0
Controls Output Amplitude
RW
RW
00 = 0.6V
10= 0.8V
1. A low on the DIF OE bit will overide the OE# pin and force the differential output Low/Low
SMBus Table: DIF Slew Rate Control Register
Byte 2
Name
Control Function
Bit 7
Reserved
Bit 6
SLEWRATESEL DIF3
Slew Rate Selection
Bit 5
SLEWRATESEL DIF2
Slew Rate Selection
Bit 4
Reserved
Bit 3
SLEWRATESEL DIF1
Slew Rate Selection
Bit 2
Reserved
Bit 1
SLEWRATESEL DIF0
Slew Rate Selection
Bit 0
Reserved
Type
RW
RW
RW
RW
0
Slow setting
Slow setting
Slow setting
Slow setting
SMBus Table: DIF Slew Rate Control Register
Byte 3
Name
Control Function
Bit 7
Reserved
Bit 6
Reserved
Bit 5
Reserved
Bit 4
Reserved
Bit 3
Reserved
Bit 2
Bit 1
Bit 0
SLEWRATESEL DIF4
Reserved
Reserved
Adjust Slew Rate of DIF4
Type
RW
0
Slow setting
Byte 4 is Reserved and reads back 'hFF
1
Enabled
Enabled
Enabled
Enabled
Default
1
1
1
1
1
1
1
1
1
Enabled
01 = 0.7V
11 = 0.9V
Default
0
1
1
0
1
1
1
0
1
Fast setting
Fast setting
Fast setting
Fast setting
Default
1
1
1
1
1
1
1
1
1
Fast setting
Default
1
1
0
0
0
1
1
1
REVISION B 08/28/14
11 5 O/P 1.8V PCIE GEN1-2-3 FAN-OUT BUFFER W/ZO=100OHMS
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet 9DBV0541.PDF ] | |
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