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9DBV0741 데이터시트 PDF




IDT에서 제조한 전자 부품 9DBV0741은 전자 산업 및 응용 분야에서
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부품번호 9DBV0741 기능
기능 7-output 1.8V HCSL Fanout Buffer
제조업체 IDT
로고 IDT 로고


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9DBV0741 데이터시트, 핀배열, 회로
7-output 1.8V HCSL Fanout Buffer
w/Zo=100ohms
9DBV0741
DATASHEET
Description
The 9DBV0741 is a member of IDT's Full-Featured PCIe
family. The device has 7 output enables for clock
management, and 3 selectable SMBus addresses. It has
integrated terminations for direct connection to 100ohm
transmission lines.
Recommended Application
PCIe Gen1-3 clock distribution in Storage, Networking,
Compute, Consumer
Output Features
7 – 1-200MHz Low-Power (LP) HCSL DIF pairs
w/ZO=100
Easy AC-coupling to other logic families, see IDT
application note AN-891
Key Specifications
Additive cycle-to-cycle jitter <5ps
Output-to-output skew < 60ps
Additive phase jitter is <100fs rms for PCIe Gen3
Additive phase jitter <300fs rms (12kHz-20MHz @125MHz)
Block Diagram
vOE(6:0)#
7
CLK_IN
CLK_IN#
vSADR
^CKPWRGD_PD#
SDATA_3.3
SCLK_3.3
CONTROL
LOGIC
Features/Benefits
100ohm direct connect; saves 28 resistors and 48mm2
compared to standard HCSL
41mW typical power consumption; eliminates thermal
concerns
Outputs can optionally be supplied from any voltage
between 1.05V and 1.8V; maximum power savings
OE# pins; support DIF power management
HCSL-compatible differential input; can be driven by
common clock sources
SMBus-selectable features allow optimization to customer
requirements
Slew rate for each output; allows tuning for various line
lengths
Differential output amplitude; allows tuning for various
application environments
1MHz to 200MHz operating frequency
3.3V tolerant SMBus interface works with legacy controllers
Selectable SMBus addresses; multiple devices can easily
share an SMBus segment
Device contains default configuration; SMBus interface not
required for device operation
Space saving 40-pin 5x5mm VFQFPN; minimal board
space
DIF6
DIF5
DIF4
DIF3
DIF2
DIF1
DIF0
9DBV0741 REVISION B 03/28/16 1 ©2016 Integrated Device Technology, Inc.




9DBV0741 pdf, 반도체, 판매, 대치품
9DBV0741 DATASHEET
Test Loads
Low-Power HCSL Differential Output Test Load
5 inches
Rs Zo=100W
Rs
Device
2pF 2pF
Alternate Terminations
The 9DBV0741 can easily drive LVPECL, LVDS, and CML logic. See “AN-891 Driving LVPECL, LVDS, and CML Logic with IDT's
"Universal" Low-Power HCSL Outputs” for details.
7-OUTPUT 1.8V HCSL FANOUT BUFFER W/ZO=100OHMS
4
REVISION B 03/28/16

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9DBV0741 전자부품, 판매, 대치품
9DBV0741 DATASHEET
Electrical Characteristics–DIF Low-Power HCSL Outputs
TA = TCOM or TIND; Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN TYP
Slew rate
Trf
Scope averaging on, fast slew rate setting
1.6 2.6
Scope averaging on, slow slew rate setting
1.2 2.0
Slew rate matching ΔTrf Slew rate matching, Scope averaging on
6
Voltage High
Voltage Low
Max Voltage
Min Voltage
Vswing
VHIGH
VLOW
Vmax
Vmin
Vswing
Statistical measurement on single-ended signal 660 758
using oscilloscope math function. (Scope
-150 43
Measurement on single ended signal using
775
absolute value. (Scope averaging off)
-300 12
Scope averaging off
300 1428
MAX UNITS NOTES
4.3 V/ns 1,2,3
3.2 V/ns 1,2,3
20 % 1,2,4
850
150
1150
mV
mV
mV
7
7
7
7
1,2
Crossing Voltage (abs) Vcross_abs
Scope averaging off
250 391 550 mV 1,5
Crossing Voltage (var)
Δ-Vcross
Scope averaging off
1Guaranteed by design and characterization, not 100% tested in production. CL = 2pF.
2 Measured from differential waveform
14 140 mV 1,6
3 Slew rate is measured through the Vswing voltage range centered around differential 0V. This results in a +/-150mV window around
differential 0V.
4 Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/-75mV window centered on
the average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the
oscilloscope is to use for the edge rate calculations.
5 Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising
edge (i.e. Clock rising and Clock# falling).
6 The total variation of all Vcross measurements in any particular system. Note that this is a subset of Vcross_min/max (Vcross
absolute) allowed. The intent is to limit Vcross induced modulation by setting Δ-Vcross to be smaller than Vcross absolute.
7 660mV Vhigh is the minimum when VDDIO is >= 1.05V +/-5%. If VDDIO is < 1.05V +/-5%, the minimum Vhigh will be VDDIOmin -
250mV. For example for VDDIO = 0.9V +/-5%, VHIGHmin will be 860mV - 250mV = 610mV.
Electrical Characteristics–Current Consumption
TA = TCOM or TIND; Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN TYP
IDDR VDDR @100MHz
Operating Supply Current
IDDDIG
VDDIG, All outputs @100MHz
IDDO VDD1.8+VDDIO, All outputs @100MHz
Powerdown Current
IDDRPD
IDDDIGPD
IDDOPD
VDDR, CKPWRGD_PD# = 0
VDDDIG, CKPWRGD_PD# = 0
VDD1.8+VDDIO, CKPWRGD_PD# = 0
1 Guaranteed by design and characterization, not 100% tested in production.
2 Input clock stopped.
3
5
26
0.4
0.5
0.001
MAX
5
8
32
1
1
0.1
UNITS
mA
mA
mA
mA
mA
mA
NOTES
1
1
1
1,2
1, 2
1, 2
REVISION B 03/28/16
7 7-OUTPUT 1.8V HCSL FANOUT BUFFER W/ZO=100OHMS

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부품번호상세설명 및 기능제조사
9DBV0741

7-output 1.8V HCSL Fanout Buffer

IDT
IDT

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