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9DBV0931 데이터시트 PDF




IDT에서 제조한 전자 부품 9DBV0931은 전자 산업 및 응용 분야에서
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부품번호 9DBV0931 기능
기능 9-output 1.8V HCSL Fanout Buffer
제조업체 IDT
로고 IDT 로고


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9DBV0931 데이터시트, 핀배열, 회로
9-output 1.8V HCSL Fanout Buffer
9DBV0931
DATASHEET
Description
The 9DBV0931 is a member of IDT's Full-Featured PCIe
family. The device has 9 output enables for clock
management, and 3 selectable SMBus addresses.
Recommended Application
PCIe Gen1-3 clock distribution in Storage, Networking,
Compute, Consumer
Output Features
9 - 1-200MHz Low-Power (LP) HCSL DIF pairs
Key Specifications
Additive cycle-to-cycle jitter <5ps
Output-to-output skew < 60ps
Additive phase jitter is <100fs rms for PCIe Gen3
Additive phase jitter <300fs rms (12kHz-20MHz @125MHz)
Block Diagram
Features/Benefits
LP-HCSL outputs; save 18 resistors and 31mm2 compared
to standard HCSL
53mW typical power consumption; eliminates thermal
concerns
Outputs can optionally be supplied from any voltage
between 1.05V and 1.8V; maximum power savings
OE# pins; support DIF power management
HCSL-compatible differential input; can be driven by
common clock sources
SMBus-selectable features allow optimization to customer
requirements
Slew rate for each output; allows tuning for various line
lengths
Differential output amplitude; allows tuning for various
application environments
1MHz to 200MHz operating frequency
3.3V tolerant SMBus interface works with legacy controllers
Selectable SMBus addresses; multiple devices can easily
share an SMBus segment
Device contains default configuration; SMBus interface not
required for device operation
Space saving 48-pin 6x6mm VFQFPN; minimal board
space
vOE(8:0)#
9
CLK_IN
CLK_IN#
vSADR
^CKPWRGD_PD#
SDATA_3.3
SCLK_3.3
CONTROL
LOGIC
DIF8
DIF7
DIF6
DIF5
DIF4
DIF3
DIF2
DIF1
DIF0
9DBV0931 REVISION D 03/28/16 1 ©2016 Integrated Device Technology, Inc.




9DBV0931 pdf, 반도체, 판매, 대치품
9DBV0931 DATASHEET
Pin Descriptions (cont.)
PIN #
PIN NAME
40 GND
41 DIF6
42 DIF6#
TYPE
GND
OUT
OUT
43 vOE6#
IN
44 DIF7
45 DIF7#
OUT
OUT
46 vOE7#
IN
47 VDDIO
PWR
48 ^CKPWRGD_PD#
IN
49 epad
GND
DESCRIPTION
Ground pin.
Differential true clock output
Differential Complementary clock output
Active low input for enabling DIF pair 6. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
Differential true clock output
Differential Complementary clock output
Active low input for enabling DIF pair 7. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
Power supply for differential outputs
Input notifies device to sample latched inputs and start up on first high
assertion. Low enters Power Down Mode, subsequent high assertions exit
Power Down Mode. This pin has internal pull-up resistor.
Connect epad to ground.
9-OUTPUT 1.8V HCSL FANOUT BUFFER
4
REVISION D 03/28/16

4페이지










9DBV0931 전자부품, 판매, 대치품
9DBV0931 DATASHEET
Electrical Characteristics–Input/Supply/Common Parameters–Normal Operating
Conditions
TA = TCOM or TIND; Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN TYP
MAX UNITS NOTES
Supply Voltage
VDDx
Supply voltage for core and analog
Output Supply Voltage VDDIO
Low Voltage Supply LP-HCSL Outputs
Ambient Operating
Temperature
Input High Voltage
Input Mid Voltage
Input Low Voltage
Input Current
Input Frequency
Pin Inductance
Capacitance
Clk Stabilization
TCOM
TIND
VIH
VIM
VIL
IIN
IINP
Fin
Lpin
CIN
CINDIF_IN
COUT
TSTAB
Commmercial range
Industrial range
Single-ended inputs, except SMBus
Single-ended tri-level inputs ('_tri' suffix)
Single-ended inputs, except SMBus
Single-ended inputs, VIN = GND, VIN = VDD
Single-ended inputs
VIN = 0 V; Inputs with internal pull-up resistors
VIN = VDD; Inputs with internal pull-down resistors
Logic Inputs, except DIF_IN
DIF_IN differential clock inputs
Output pin capacitance
From VDD Power-Up and after input clock
stabilization or de-assertion of PD# to 1st clock
Input SS Modulation
Frequency PCIe
fMODINPCIe
Allowable Frequency for PCIe Applications
(Triangular Modulation)
Input SS Modulation
Frequency non-PCIe
fMODIN
Allowable Frequency for non-PCIe Applications
(Triangular Modulation)
OE# Latency
tLATOE#
DIF start after OE# assertion
DIF stop after OE# deassertion
Tdrive_PD#
tDRVPD
DIF output enable after
PD# de-assertion
Tfall
Trise
SMBus Input Low Voltage
SMBus Input High Voltage
SMBus Output Low Voltage
SMBus Sink Current
Nominal Bus Voltage
SCLK/SDATA Rise Time
SCLK/SDATA Fall Time
SMBus Operating
Frequency
tF
tR
VILSMB
VIHSMB
VOLSMB
IPULLUP
VDDSMB
tRSMB
tFSMB
fMAXSMB
Fall time of single-ended control inputs
Rise time of single-ended control inputs
VDDSMB = 3.3V, see note 4 for VDDSMB < 3.3V
VDDSMB = 3.3V, see note 5 for VDDSMB < 3.3V
@ IPULLUP
@ VOL
Bus Voltage
(Max VIL - 0.15) to (Min VIH + 0.15)
(Min VIH + 0.15) to (Max VIL - 0.15)
Maximum SMBus operating frequency
1Guaranteed by design and characterization, not 100% tested in production.
2Control input must be monotonic from 20% to 80% of input swing.
3Time from deassertion until outputs are >200 mV
4 For VDDSMB < 3.3V, VILSMB <= 0.35VDDSMB
5 For VDDSMB < 3.3V, VIHSMB >= 0.65VDDSMB
6DIF_IN input
7The differential input clock must be running for the SMBus to be active
1.7
0.9975
0
-40
0.75 VDD
0.4 VDD
-0.3
-5
1.8
1.05-1.8
25
25
1.9
1.9
70
85
VDD + 0.3
0.6 VDD
0.25 VDD
5
V
V
°C
°C
V
V
V
uA
-200
200 uA
1 200 MHz
7 nH
1.5 5 pF
1.5 2.7 pF
6 pF
1 ms
30 33 kHz
0 66 kHz
1 3 clocks
300 us
5 ns
5 ns
0.8 V
2.1 3.3 V
0.4 V
4 mA
1.7 3.6 V
1000
ns
300 ns
400 kHz
1
1
2
1
1
1,6
1
1,2
1,3
1,3
2
2
4
5
1
1
7
REVISION D 03/28/16
7 9-OUTPUT 1.8V HCSL FANOUT BUFFER

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부품번호상세설명 및 기능제조사
9DBV0931

9-output 1.8V HCSL Fanout Buffer

IDT
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