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9DBL08 데이터시트 PDF




IDT에서 제조한 전자 부품 9DBL08은 전자 산업 및 응용 분야에서
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부품번호 9DBL08 기능
기능 8-output 3.3V PCIe Zero-Delay Buffer
제조업체 IDT
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9DBL08 데이터시트, 핀배열, 회로
8-output 3.3V PCIe Zero-Delay Buffer
9DBL08
Description
The 9DBL08 devices are 3.3V members of IDT's
Full-Featured PCIe family. The 9DBL08 supports PCIe
Gen1-4 Common Clocked (CC) and PCIe Separate
Reference Independent Spread (SRIS) systems. It offers a
choice of integrated output terminations providing direct
connection to 85or 100transmission lines. The
9DBL08P1 can be factory programmed with a user-defined
power up default SMBus configuration.
Recommended Application
PCIe Gen1-4 clock distribution for Riser Cards, Storage,
Networking, JBOD, Communications, Access Points
Output Features
8 – 1-200 MHz Low-Power (LP) HCSL DIF pairs
9DBL0841 default ZOUT = 100
9DBL0851 default ZOUT = 85
9DBL08P1 factory programmable defaults
Easy AC-coupling to other logic families, see IDT
application note AN-891
Key Specifications
PCIe Gen1-2-3-4 CC compliant in ZDB mode
PCIe Gen2 SRIS compliant in ZDB mode
Supports PCIe Gen2-3 SRIS in fan-out mode
DIF cycle-to-cycle jitter <50ps
DIF output-to-output skew < 50ps
Bypass mode additive phase jitter is 0 ps typical rms for
PCIe
Bypass mode additive phase jitter 160fs rms typ. @
156.25M (1.5M to 10M)
Block Diagram
DATASHEET
Features/Benefits
Direct connection to 100(0841) or 85(0851)
transmission lines; saves 32 resistors compared to
standard PCIe devices
211mW typical power consumption (PLL [email protected]);
eliminates thermal concerns
VDDIO allows 35% power savings at optional 1.05V;
maximum power savings
SMBus-selectable features allows optimization to customer
requirements:
control input polarity
control input pull up/downs
slew rate for each output
differential output amplitude
output impedance for each output
50, 100, 125MHz operating frequency
Customer defined SMBus power up default can be
programmed into P1 device; allows exact optimization to
customer requirements
OE# pins; support DIF power management
HCSL-compatible differential input; can be driven by
common clock sources
Spread Spectrum tolerant; allows reduction of EMI
Pin/SMBus selectable PLL bandwidth and PLL Bypass;
minimize phase jitter for each application
Outputs blocked until PLL is locked; clean system start-up
Device contains default configuration; SMBus interface not
required for device operation
Three selectable SMBus addresses; multiple devices can
easily share an SMBus segment
Space saving 48-pin 6x6mm VFQFPN; minimal board
space
vOE(7:0)#
XIN/CLKIN_25
X2
OSC
vSADR
vSS_EN_tri
^CKPWRGD_PD#
SDATA_3.3
SCLK_3.3
CONTROL
LOGIC
SS Capable PLL
REF3.3
DIF7
DIF6
DIF5
DIF4
DIF3
DIF2
DIF1
DIF0
Note: Resistors default to internal on 41/51 devices. P1 devices have programmable default impedances on an output-by-output basis.
9DBL08 REVISION D 08/16/16
1 ©2016 Integrated Device Technology, Inc.




9DBL08 pdf, 반도체, 판매, 대치품
9DBL08 DATASHEET
Pin Descriptions (cont.)
PIN #
PIN NAME
40 GND
41 DIF6
42 DIF6#
TYPE
GND
OUT
OUT
43 vOE6#
IN
44 DIF7
45 DIF7#
OUT
OUT
46 vOE7#
IN
47 VDDIO
PWR
48 ^CKPWRGD_PD#
IN
49 EPAD
GND
DESCRIPTION
Ground pin.
Differential true clock output
Differential Complementary clock output
Active low input for enabling output 6. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
Differential true clock output
Differential Complementary clock output
Active low input for enabling output 7. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
Power supply for differential outputs
Input notifies device to sample latched inputs and start up on first high
assertion. Low enters Power Down Mode, subsequent high assertions exit
Power Down Mode. This pin has internal pull-up resistor.
Connect to Ground.
Test Loads
Low-Power push-pull HCSL Output test load
(integrated terminations)
L inches
Differential Zo
2pF 2pF
Terminations
Device
9DBL0841
9DBL0851
9DBL08P1
9DBL0841
9DBL0851
9DBL08P1
Zo ()
100
100
100
85
85
85
Rs ()
None needed
7.5
Prog.
N/A
None needed
Prog.
Alternate Terminations
The 9DBL family can easily drive LVPECL, LVDS, and CML logic. See “AN-891 Driving LVPECL, LVDS, and CML Logic with
IDT's "Universal" Low-Power HCSL Outputs” for details.
8-OUTPUT 3.3V PCIE ZERO-DELAY BUFFER
4
REVISION D 08/16/16

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9DBL08 전자부품, 판매, 대치품
9DBL08 DATASHEET
Electrical Characteristics–DIF Low-Power HCSL Outputs
TA = TAMB, Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
Slew rate
Slew rate matching
SYMBOL
dV/dt
dV/dt
ΔdV/dt
CONDITIONS
Scope averaging on, fast setting
Scope averaging on, slow setting
Slew rate matching
MIN TYP MAX UNITS NOTES
2 2.8 4 V/ns 1,2,3
1.2 1.9 3.1 V/ns 1,2,3
7 20 % 1,2,4
Voltage High
Voltage Low
VHIGH
VLOW
Statistical measurement on single-ended signal 660 768 850
using oscilloscope math function. (Scope
mV
averaging on)
-150 -11 150
7
7
Max Voltage
Min Voltage
Vmax
Vmin
Measurement on single ended signal using
absolute value. (Scope averaging off)
-300
811
-49
1150 mV
7
7
Crossing Voltage (abs) Vcross_abs
Scope averaging off
250 357 550 mV 1,5
Crossing Voltage (var)
Δ-Vcross
Scope averaging off
14 140 mV 1,6
1Guaranteed by design and characterization, not 100% tested in production.
2 Measured from differential waveform
3 Slew rate is measured through the Vswing voltage range centered around differential 0V. This results in a +/-150mV window around
differential 0V.
4 Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/-75mV window centered on
the average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the
oscilloscope is to use for the edge rate calculations.
5 Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising
edge (i.e. Clock rising and Clock# falling).
6 The total variation of all Vcross measurements in any particular system. Note that this is a subset of Vcross_min/max (Vcross
absolute) allowed. The intent is to limit Vcross induced modulation by setting Δ-Vcross to be smaller than Vcross absolute.
7 At default SMBus settings.
Electrical Characteristics–Current Consumption
TA = TAMB, Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN
IDDA VDDA, PLL Mode, @100MHz
Operating Supply Current
IDD
VDDx, All outputs active @100MHz
IDDIO
VDDIO, All outputs active @100MHz
Powerdown Current
IDDAPD
IDDPD
VDDA, CKPWRGD_PD#=0
VDDx, CKPWRGD_PD#=0
IDDIOPD
VDDIO, CKPWRGD_PD#=0
1 Guaranteed by design and characterization, not 100% tested in production.
2 Input clock stopped.
TYP
7
22
35
0.6
4.9
0.04
MAX
10
32
45
1
7
0.10
UNITS
mA
mA
mA
mA
mA
mA
NOTES
2
2
2
REVISION D 08/16/16
7 8-OUTPUT 3.3V PCIE ZERO-DELAY BUFFER

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