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9DBV0431 데이터시트 PDF




IDT에서 제조한 전자 부품 9DBV0431은 전자 산업 및 응용 분야에서
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부품번호 9DBV0431 기능
기능 4-output 1.8V PCIe Gen1-2-3 Zero-delay/Fanout Buffer
제조업체 IDT
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9DBV0431 데이터시트, 핀배열, 회로
4-output 1.8V PCIe Gen1-2-3
Zero-delay/Fanout Buffer (ZDB/FOB)
9DBV0431
DATASHEET
Description
The 9DBV0431 is a member of IDT's SOC-Friendly 1.8V
Very-Low-Power (VLP) PCIe family. It can also be used for
50M or 125M Ethernet Applications via software frequency
selection. The device has 4 output enables for clock
management, and 3 selectable SMBus addresses.
Recommended Application
1.8V PCIe Gen1-2-3 Zero-Delay/Fan-out Buffer (ZDB/FOB)
Output Features
4 - 1-200Hz Low-Power (LP) HCSL DIF pairs
w/ZO=100ohms
Key Specifications
DIF cycle-to-cycle jitter <50ps
DIF output-to-output skew <50ps
DIF additive phase jitter is <100fs rms for PCIe Gen3
DIF additive phase jitter <300fs rms for 12k-20MHz
Block Diagram
Features/Benefits
LP-HCSL outputs save 8 resistors; minimal board space
and BOM cost
53mW typical power consumption in PLL mode; minimal
power consumption
OE# pins; support DIF power management
HCSL compatible differential input; can be driven by
common clock sources
Programmable Slew rate for each output; allows tuning for
various line lengths
Programmable output amplitude; allows tuning for various
application environments
Pin/software selectable PLL bandwidth and PLL Bypass;
minimize phase jitter for each application
Outputs blocked until PLL is locked; clean system start-up
Software selectable 50MHz or 125MHz PLL operation;
useful for Ethernet applications
Configuration can be accomplished with strapping pins;
SMBus interface not required for device control
3.3V tolerant SMBus interface works with legacy controllers
Space saving 32-pin 5x5mm VFQFPN; minimal board
space
Selectable SMBus addresses; multiple devices can easily
share an SMBus segment
vOE(3:0)#
4
CLK_IN
CLK_IN#
vSADR
^vHIBW_BYPM_LOBW#
^CKPWRGD_PD#
SDATA_3.3
SCLK_3.3
SS-
Compatible
PLL
CONTROL
LOGIC
DIF3
DIF2
DIF1
DIF0
9DBV0431 REVISION E 04/28/16 1 ©2016 Integrated Device Technology, Inc.




9DBV0431 pdf, 반도체, 판매, 대치품
9DBV0431 DATASHEET
Test Loads
Low-Power Differential Output Test Load
Rs
Rs
5 inches
Zo=100ohm
2pF 2pF
Alternate Differential Output Terminations
Rs Zo Units
33
27
100
85
Ohms
Driving LVDS
Driving LVDS
3.3 Volts
Rs
Rs
Cc
Cc
R7a R7b
L4
R8a R8b
LVDS CLK
Input
Driving LVDS inputs with the 9DBV0431
Value
Receiver has Receiver does not
Component
termination have termination Note
R7a, R7b
10K ohm
140 ohm
R8a, R8b
5.6K ohm
75 ohm
Cc
0.1 uF
0.1 uF
Vcm
1.2 volts
1.2 volts
4-OUTPUT 1.8V PCIE GEN1-2-3 ZERO-DELAY/FANOUT BUFFER (ZDB/FOB) 4
REVISION E 04/28/16

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9DBV0431 전자부품, 판매, 대치품
9DBV0431 DATASHEET
Electrical Characteristics–DIF 0.7V Low Power HCSL Outputs
TA = TCOM or TIND; Supply Voltage per VDD of normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
Slew rate
Slew rate matching
SYMBOL
Trf
ΔTrf
CONDITIONS
Scope averaging on 3.0V/ns setting
Scope averaging on 2.0V/ns setting
Slew rate matching, Scope averaging on
MIN TYP MAX UNITS NOTES
2 3.2 4 V/ns 1, 2, 3
1.3 2.3 3.3 V/ns 1, 2, 3
5.4 20 % 1, 2, 4
Voltage High
Voltage Low
VHIGH
VLOW
Statistical measurement on single-ended signal 660 779 850
using oscilloscope math function. (Scope
mV
averaging on)
-150 21 150
1,7
1,7
Max Voltage
Min Voltage
Vmax
Vmin
Measurement on single ended signal using
absolute value. (Scope averaging off)
835 1150 mV
-300 -42
1
1
Vswing
Vswing
Scope averaging off
300 1515
mV 1,2,7
Crossing Voltage (abs) Vcross_abs
Scope averaging off
250 409 550 mV 1,5,7
Crossing Voltage (var)
Δ-Vcross
Scope averaging off
14 140 mV 1, 6
1Guaranteed by design and characterization, not 100% tested in production. CL = 2pF with RS = 33for Zo = 50(100differential
trace impedance).
2 Measured from differential waveform
3 Slew rate is measured through the Vswing voltage range centered around differential 0V. This results in a +/-150mV window around
differential 0V.
4 Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/-75mV window centered on
the average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the
oscilloscope is to use for the edge rate calculations.
5 Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising
edge (i.e. Clock rising and Clock# falling).
6 The total variation of all Vcross measurements in any particular system. Note that this is a subset of Vcross_min/max (Vcross
absolute) allowed. The intent is to limit Vcross induced modulation by setting -Vcross to be smaller than Vcross absolute.
7 At default SMBus settings.
Electrical Characteristics–Current Consumption
TA = TCOM or TIND; Supply Voltage per VDD of normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX
Operating Supply Current
(PLL Mode)
IDDROP
IDDOP
VDDR, @100MHz
VDDA + VDD1.8, @100MHz
Operating Supply Current
(PLL-Bypass Mode)
IDDROP
IDDOP
VDDR, @100MHz
VDDA + VDD1.8, @100MHz
Powerdown Current
IDDRPD
IDDPD
VDDR, CKPWRGD_PD# = 0
VDDA + VDD1.8, CKPWRGD_PD# = 0
1 Guaranteed by design and characterization, not 100% tested in production.
2 Input clock stopped, and CKPWRGD_PD# pin low.
4.2
27
2.2
20
0.014
0.95
6
33
3
25
0.3
1.2
UNITS
mA
mA
mA
mA
mA
mA
NOTES
1
1
1
1
1,2
1, 2
REVISION E 04/28/16
7 4-OUTPUT 1.8V PCIE GEN1-2-3 ZERO-DELAY/FANOUT BUFFER (ZDB/FOB)

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부품번호상세설명 및 기능제조사
9DBV0431

4-output 1.8V PCIe Gen1-2-3 Zero-delay/Fanout Buffer

IDT
IDT

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