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부품번호 | 9DBV0531 기능 |
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기능 | 5-output 1.8V HCSL Fanout Buffer | ||
제조업체 | IDT | ||
로고 | |||
전체 17 페이지수
5-output 1.8V HCSL Fanout Buffer
9DBV0531
DATASHEET
Description
The 9DBV0531 is a member of IDT's Full-Featured PCIe
family. The device has 5 output enables for clock
management, and 3 selectable SMBus addresses.
Recommended Application
PCIe Gen1-3 clock distribution in Storage, Networking,
Computing, Consumer
Output Features
• 5 - 1-200MHz Low-Power (LP) HCSL DIF pairs
• Easy AC-coupling to other logic families, see IDT
application note AN-891
Key Specifications
• Additive cycle-to-cycle jitter <5ps
• Output-to-output skew < 50ps
• Additive phase jitter is <100fs rms for PCIe Gen3
• Additive phase jitter <300fs rms (12kHz-20MHz @125MHz)
Features/Benefits
• LP-HCSL outputs; save 10 resistors and 17mm2 compared
to standard HCSL
• 50mW typical power consumption; eliminates thermal
concerns
• OE# pin for each output; support DIF power management
• HCSL differential input; can be driven by common clock
sources
• Spread Spectrum tolerant; allows reduction of EMI
• SMBus-selectable features allow optimization to customer
requirements
• Slew rate for each output; allows tuning for various line
lengths
• Differential output amplitude; allows tuning for various
application environments
• 1MHz to 200MHz operating frequency
• 3.3V tolerant SMBus interface works with legacy controllers
• Selectable SMBus addresses; multiple devices can easily
share an SMBus segment
• Device contains default configuration; SMBus interface not
required for device operation
• Space saving 32-pin 5x5mm VFQFPN; minimal board
space
Block Diagram
vOE(4:0)#
5
CLK_IN
CLK_IN#
vSADR
^CKPWRGD_PD#
SDATA_3.3
SCLK_3.3
CONTROL
LOGIC
DIF4
DIF3
DIF2
DIF1
DIF0
9DBV0531 REVISION E 05/23/16 1 ©2016 Integrated Device Technology, Inc.
9DBV0531 DATASHEET
Test Loads
Low-Power Differential Output Test Load
Rs
Rs
5 inches
Zo=100ohm
2pF 2pF
Alternate Differential Output Terminations
Rs Zo Units
33
27
100
85
Ohms
Alternate Terminations
The 9DBV0531 can easily drive LVPECL, LVDS, and CML logic. See “AN-891 Driving LVPECL, LVDS, and CML Logic with IDT's
"Universal" Low-Power HCSL Outputs” for details.
5-OUTPUT 1.8V HCSL FANOUT BUFFER
4
REVISION E 05/23/16
4페이지 9DBV0531 DATASHEET
Electrical Characteristics–DIF Low-Power HCSL Outputs
TA = TCOM or TIND; Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS NOTES
Slew rate
Slew rate matching
dV/dt
dV/dt
ΔdV/dt
Scope averaging on, fast setting
Scope averaging on, slow setting
Slew rate matching, Scope averaging on
2.3 3.4 4.3 V/ns 1,2,3
1.4 2.2 3.1 V/ns 1,2,3
5 20 % 1,2,4
Voltage High
Voltage Low
VHIGH
VLOW
Statistical measurement on single-ended signal 660 774 850
using oscilloscope math function. (Scope
mV
averaging on)
-150 0 150
7
7
Max Voltage
Min Voltage
Vmax
Vmin
Measurement on single ended signal using
absolute value. (Scope averaging off)
813 1150 mV
-300 -55
7
7
Vswing
Vswing
Scope averaging off
300 1548
mV 1,2
Crossing Voltage (abs) Vcross_abs
Scope averaging off
250 404 550 mV 1,5
Crossing Voltage (var)
Δ-Vcross
Scope averaging off
12 140 mV 1,6
1Guaranteed by design and characterization, not 100% tested in production.
2 Measured from differential waveform
3 Slew rate is measured through the Vswing voltage range centered around differential 0V. This results in a +/-150mV window around
differential 0V.
4 Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/-75mV window centered on
the average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the
oscilloscope is to use for the edge rate calculations.
5 Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising
edge (i.e. Clock rising and Clock# falling).
6 The total variation of all Vcross measurements in any particular system. Note that this is a subset of Vcross_min/max (Vcross
absolute) allowed. The intent is to limit Vcross induced modulation by setting Δ-Vcross to be smaller than Vcross absolute.
7 At default SMBus settings.
Electrical Characteristics–Current Consumption
TA = TCOM or TIND; Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN TYP
IDDR VDDR @100MHz
Operating Supply Current
IDDDIG
VDDIG, All outputs @100MHz
IDDO VDD1.8, All outputs @100MHz
IDDRPD
VDDR, CKPWRGD_PD# = 0
Powerdown Current
IDDDIGPD
IDDOPD
VDDDIG, CKPWRGD_PD# = 0
VDD1.8, CKPWRGD_PD# = 0
1 Guaranteed by design and characterization, not 100% tested in production.
2 Input clock stopped.
2
0.2
23
0.001
0.17
0.4
MAX
3
0.5
27
0.1
0.3
0.8
UNITS
mA
mA
mA
mA
mA
mA
NOTES
2
2
2
REVISION E 05/23/16
7 5-OUTPUT 1.8V HCSL FANOUT BUFFER
7페이지 | |||
구 성 | 총 17 페이지수 | ||
다운로드 | [ 9DBV0531.PDF 데이터시트 ] |
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부품번호 | 상세설명 및 기능 | 제조사 |
9DBV0531 | 5-output 1.8V HCSL Fanout Buffer | IDT |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |