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9DBV0631 데이터시트 PDF




IDT에서 제조한 전자 부품 9DBV0631은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


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부품번호 9DBV0631 기능
기능 6-output 1.8V PCIe Gen1-2-3 ZDB/FOB
제조업체 IDT
로고 IDT 로고


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9DBV0631 데이터시트, 핀배열, 회로
6-output 1.8V PCIe Gen1-2-3 ZDB/FOB
9DBV0631
DATASHEET
Description
The 9DBV0631 is a member of IDT's 1.8V Very-Low-Power
(VLP) PCIe family. The device has 6 output enables for clock
management and 3 selectable SMBus addresses.
Recommended Application
1.8V PCIe Gen1-2-3 Zero Delay/Fanout Buffer (ZDB/FOB)
Output Features
6 - 1-200 MHz Low-Power (LP) HCSL DIF pairs
Key Specifications
DIF additive cycle-to-cycle jitter <5ps
DIF output-to-output skew <60ps
DIF additive phase jitter is <100fs rms for PCIe Gen3
DIF additive phase jitter <300fs rms for SGMII
Block Diagram
Features/Benefits
LP-HCSL outputs; save 12 resistors compared to standard
PCIe devices
55mW typical power consumption in PLL mode; minimal
power consumption
Outputs can optionally be supplied from any voltage
between 1.05 and 1.8V; maximum power savings
OE# pins; support DIF power management
HCSL-compatible differential input; can be driven by
common clock sources
Spread Spectrum tolerant; allows reduction of EMI
Programmable Slew rate for each output; allows tuning for
various line lengths
Programmable output amplitude; allows tuning for various
application environments
Pin/software selectable PLL bandwidth and PLL Bypass;
minimize phase jitter for each application
Outputs blocked until PLL is locked; clean system start-up
Configuration can be accomplished with strapping pins;
SMBus interface not required for device control
3.3V tolerant SMBus interface works with legacy
controllers
Space saving 40-pin 5x5mm MLF; minimal board space
3 selectable SMBus addresses; multiple devices can easily
share an SMBus segment
vOE(5:0)#
6
CLK_IN
CLK_IN#
vSADR
^vHIBW_BYPM_LOBW#
^CKPWRGD_PD#
SDATA_3.3
SCLK_3.3
SS-
Compatible
PLL
CONTROL
LOGIC
DIF5
DIF4
DIF3
DIF2
DIF1
DIF0
9DBV0631 REVISION H 07/27/16 1 ©2016 Integrated Device Technology, Inc.




9DBV0631 pdf, 반도체, 판매, 대치품
9DBV0631 DATASHEET
Pin Descriptions
PIN #
PIN NAME
PIN TYPE
DESCRIPTION
1 vSADR_tri
2 ^vHIBW_BYPM_LOBW#
3 FB_DNC
4 FB_DNC#
5 VDDR1.8
6 CLK_IN
7 CLK_IN#
8 GNDDIG
9 SCLK_3.3
10 SDATA_3.3
11 VDDDIG1.8
12 VDDIO
13 vOE0#
14 DIF0
15 DIF0#
16 VDD1.8
17 VDDIO
18 DIF1
19 DIF1#
20 NC
21 vOE1#
22 DIF2
23 DIF2#
24 vOE2#
25 VDDA1.8
26 VDDIO
27 DIF3
28 DIF3#
29 vOE3#
30 NC
31 VDD1.8
32 VDDIO
33 DIF4
34 DIF4#
35 vOE4#
36 DIF5
37 DIF5#
38 vOE5#
39 VDDIO
40 ^CKPWRGD_PD#
41 ePAD
LATCHED Tri-level latch to select SMBus Address. See SMBus Address Selection Table.
IN
LATCHED Trilevel input to select High BW, Bypass or Low BW mode.
IN See PLL Operating Mode Table for Details.
DNC True clock of differential feedback. The feedback output and feedback input are connected
internally on this pin. Do not connect anything to this pin.
DNC Complement clock of differential feedback. The feedback output and feedback input are
connected internally on this pin. Do not connect anything to this pin.
PWR
1.8V power for differential input clock (receiver). This VDD should be treated as an Analog
power rail and filtered appropriately.
IN True Input for differential reference clock.
IN Complementary Input for differential reference clock.
GND Ground pin for digital circuitry
IN Clock pin of SMBus circuitry, 3.3V tolerant.
I/O Data pin for SMBus circuitry, 3.3V tolerant.
PWR 1.8V digital power (dirty power)
PWR Power supply for differential outputs
IN
Active low input for enabling DIF pair 0. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
OUT Differential true clock output
OUT Differential Complementary clock output
PWR Power supply, nominal 1.8V
PWR Power supply for differential outputs
OUT Differential true clock output
OUT Differential Complementary clock output
N/A No Connection.
Active low input for enabling DIF pair 1. This pin has an internal pull-down.
IN 1 =disable outputs, 0 = enable outputs
OUT Differential true clock output
OUT Differential Complementary clock output
Active low input for enabling DIF pair 2. This pin has an internal pull-down.
IN 1 =disable outputs, 0 = enable outputs
PWR 1.8V power for the PLL core.
PWR Power supply for differential outputs
OUT Differential true clock output
OUT Differential Complementary clock output
Active low input for enabling DIF pair 3. This pin has an internal pull-down.
IN 1 =disable outputs, 0 = enable outputs
N/A No Connection.
PWR Power supply, nominal 1.8V
PWR Power supply for differential outputs
OUT Differential true clock output
OUT Differential Complementary clock output
IN Active low input for enabling DIF pair 4. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
OUT Differential true clock output
OUT Differential Complementary clock output
IN
Active low input for enabling DIF pair 5. This pin has an internal pull-down.
1 =disable outputs, 0 = enable outputs
PWR Power supply for differential outputs
Input notifies device to sample latched inputs and start up on first high assertion. Low enters
IN Power Down Mode, subsequent high assertions exit Power Down Mode. This pin has internal
pull-up resistor.
GND Connect paddle to ground.
6-OUTPUT 1.8V PCIE GEN1-2-3 ZDB/FOB
4
REVISION H 07/27/16

4페이지










9DBV0631 전자부품, 판매, 대치품
9DBV0631 DATASHEET
Electrical Characteristics–Input/Supply/Common Parameters–Normal Operating
Conditions
TA = TAMB, Voltage per VDD, VDDIO of normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX UNITS NOTES
Supply Voltage
Output Supply Voltage
VDDx
VDDIO
Supply voltage for core and analog
Supply voltage for Low Power HCSL Outputs
Ambient Operating
Temperature
TAMB
Commmercial range
Industrial range
Input High Voltage
Input Mid Voltage
Input Low Voltage
Input Current
Input Frequency
Pin Inductance
Capacitance
Clk Stabilization
Input SS Modulation
Frequency PCIe
Input SS Modulation
Frequency non-PCIe
OE# Latency
Tdrive_PD#
VIH
VIM
VIL
IIN
IINP
Fibyp
Fipll
Fipll
Fipll
Lpin
CIN
CINDIF_IN
COUT
TSTAB
fMODINPCIe
fMODIN
tLATOE#
tDRVPD
Single-ended inputs, except SMBus
Single-ended tri-level inputs ('_tri' suffix)
Single-ended inputs, except SMBus
Single-ended inputs, VIN = GND, VIN = VDD
Single-ended inputs
VIN = 0 V; Inputs with internal pull-up resistors
VIN = VDD; Inputs with internal pull-down resistors
Bypass mode
100MHz PLL mode
125MHz PLL mode
50MHz PLL mode
Logic Inputs, except DIF_IN
DIF_IN differential clock inputs
Output pin capacitance
From VDD Power-Up and after input clock
stabilization or de-assertion of PD# to 1st clock
Allowable Frequency for PCIe Applications
(Triangular Modulation)
Allowable Frequency for non-PCIe Applications
(Triangular Modulation)
DIF start after OE# assertion
DIF stop after OE# deassertion
DIF output enable after
PD# de-assertion
Tfall tF Fall time of single-ended control inputs
Trise
tR Rise time of single-ended control inputs
SMBus Input Low Voltage VILSMB
VDDSMB = 3.3V, see note 4 for VDDSMB < 3.3V
SMBus Input High Voltage VIHSMB
VDDSMB = 3.3V, see note 5 for VDDSMB < 3.3V
SMBus Output Low Voltage VOLSMB
@ IPULLUP
SMBus Sink Current
IPULLUP
@ VOL
Nominal Bus Voltage
VDDSMB
Bus Voltage
SCLK/SDATA Rise Time
tRSMB
(Max VIL - 0.15) to (Min VIH + 0.15)
SCLK/SDATA Fall Time
tFSMB
(Min VIH + 0.15) to (Max VIL - 0.15)
SMBus Operating
Frequency
fMAXSMB
Maximum SMBus operating frequency
1Guaranteed by design and characterization, not 100% tested in production.
2Control input must be monotonic from 20% to 80% of input swing.
3Time from deassertion until outputs are >200 mV
4 For VDDSMB < 3.3V, VILSMB <= 0.35VDDSMB
5 For VDDSMB < 3.3V, VIHSMB >= 0.65VDDSMB
6DIF_IN input
7The differential input clock must be running for the SMBus to be active
1.7
0.95
0
-40
0.75 VDD
0.4 VDD
-0.3
-5
1.8
1.05-1.8
1.9
1.9
25 70
25 85
VDD + 0.3
0.6 VDD
0.25 VDD
5
V
V
°C
°C
V
V
V
uA
-200
200 uA
1
50
62.5
25
1.5
1.5
100.00
125.00
50.00
200
140
175
65
7
5
2.7
6
1
MHz
MHz
MHz
MHz
nH
pF
pF
pF
ms
30 33 kHz
0 66 kHz
1 3 clocks
300 us
5 ns
5 ns
0.8 V
2.1 3.6 V
0.4 V
4 mA
1.7 3.6 V
1000
ns
300 ns
400 kHz
1
1
2
2
2
2
1
1
1,6
1
1,2
1,3
1,3
2
2
4
5
1
1
7
REVISION H 07/27/16
7 6-OUTPUT 1.8V PCIE GEN1-2-3 ZDB/FOB

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부품번호상세설명 및 기능제조사
9DBV0631

6-output 1.8V PCIe Gen1-2-3 ZDB/FOB

IDT
IDT

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