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PDF AD7153 Data sheet ( Hoja de datos )
| Número de pieza | AD7153 | |
| Descripción | 12-Bit Capacitance-to-Digital Converter | |
| Fabricantes | Analog Devices | |
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Data Sheet
12-Bit Capacitance-to-Digital Converter
AD7152/AD7153
FEATURES
Capacitance-to-digital converters
Interfaces to floating sensors
Resolution down to 0.25 fF (that is, up to 12 ENOB)
Linearity: 0.05%
Common-mode (not changing) capacitance up to 5 pF
Four capacitance ranges selectable per operation mode
±0.25 pF to ±2 pF in differential mode
0.5 pF to 4 pF in single-ended mode
Tolerant of parasitic capacitance to ground up to 50 pF
Conversion time per channel: 5 ms, 20 ms, 50 ms, and 60 ms
Internal clock oscillator
2-wire serial interface (I2C-compatible)
Power
2.7 V to 3.6 V single-supply operation
100 μA current consumption
Operating temperature: −40°C to +85°C
10-lead MSOP
APPLICATIONS
Automotive, industrial, and medical systems for
Pressure measurement
Position sensing
Level sensing
Flowmeters
Humidity sensing
FUNCTIONAL BLOCK DIAGRAMS
VDD
CIN1(+)
CIN1(–)
EXC1
CIN2(+)
CIN2(–)
EXC2
CAP+
CAP–
AD7152
CLOCK
VOLTAGE
GENERATOR REFERENCE
MUX
12-BIT Σ-∆
MODULATOR
I2C
SERIAL
INTERFACE
SDA
SCL
EXCITATION
DIGITAL
FILTER
CONTROL LOGIC
CALIBRATION
GND
Figure 1.
VDD
CAP+
CAP–
AD7153
CLOCK
VOLTAGE
GENERATOR REFERENCE
CIN1(+)
CIN1(–)
EXC1
MUX
12-BIT Σ-∆
MODULATOR
I2C
SERIAL
INTERFACE
SDA
SCL
EXCITATION
DIGITAL
FILTER
CONTROL LOGIC
CALIBRATION
GND
Figure 2.
GENERAL DESCRIPTION
The AD7152/AD7153 are 12-bit sigma-delta (Σ-Δ) capacitance-to-
digital converters (CDCs). The capacitance to be measured is
connected directly to the device inputs. The architecture features
inherent high resolution (12-bit no missing codes, up to 12-bit
effective resolution) and high linearity (±0.05%). The AD7152/
AD7153 have four capacitance input ranges per operation mode,
±0.25 pF to ±2 pF in differential mode and 0.5 pF to 4 pF in
single-ended mode.
The AD7152/AD7153 can accept up to 5 pF common-mode
capacitance (not changing), which can be balanced by a
programmable on-chip, digital-to-capacitance converter
(CAPDAC).
The AD7153 has one capacitance input channel, while the
AD7152 has two channels. Each channel can be configured
as single-ended or differential. The AD7152/AD7153 are
designed for floating capacitive sensors.
The AD7152/AD7153 have a 2-wire, I2C-compatible serial
interface. Both devices can operate with a single power supply
from 2.7 V to 3.6 V. They are specified over the temperature
range of −40°C to +85°C and are available in a 10-lead MSOP.
Rev. A
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2008–2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
Data Sheet
AD7152/AD7153
TIMING SPECIFICATIONS
VDD = 2.7 V to 3.6 V; GND = 0 V; Input Logic 0 = 0 V; Input Logic 1 = VDD; −40°C to +85°C, unless otherwise noted.
Table 2.
Parameter
SERIAL INTERFACE1, 2
SCL Frequency
SCL High Pulse Width, tHIGH
SCL Low Pulse Width, tLOW
SCL, SDA Rise Time, tR
SCL, SDA Fall Time, tF
Hold Time (Start Condition), tHD;STA
Set-Up Time (Start Condition), tSU;STA
Data Set-Up Time, tSU;DAT
Setup Time (Stop Condition), tSU;STO
Data Hold Time, tHD;DAT (Master)
Bus-Free Time (Between Stop and Start Conditions, tBUF)
Min Typ Max Unit Test Conditions/Comments
See Figure 3.
0 400 kHz
0.6 µs
1.3 µs
0.3 µs
0.3 µs
0.6 µs After this period, the first clock is generated.
0.6 µs Relevant for repeated start condition.
0.1 µs
0.6 µs
0.01 µs
1.3 µs
1 Sample tested during initial release to ensure compliance.
2 All input signals are specified with input rise/fall times = 3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and outputs;
output load = 10 pF.
SCL
tLOW tR
tHD;STA
tHD;DAT
SDA
tBUF
PS
tF
tHIGH
tSU;DAT
tHD;STA
tSU;STA
S
Figure 3. Serial Interface Timing Diagram
tSU;STO
P
Rev. A | Page 5 of 24
5 Page 
Data Sheet
SERIAL INTERFACE
The AD7152/AD7153 support an I2C-compatible, 2-wire serial
interface. The two wires on the I2C bus are called SCL (clock)
and SDA (data). These two wires carry all addressing, control,
and data information one bit at a time over the bus to all connected
peripheral devices. The SDA wire carries the data, while the
SCL wire synchronizes the sender and receiver during the
data transfer. I2C devices are classified as either master or slave
devices. A device that initiates a data transfer message is called a
master; a device that responds to this message is called a slave.
To control the AD7152/AD7153 via the bus, the following
protocol must be followed. The master initiates a data transfer
by establishing a start condition, defined by a high-to-low
transition on SDA while SCL remains high. This indicates that
the start byte follows. This 8-bit start byte is made up of a 7-bit
address plus an R/W bit indicator.
All peripherals connected to the bus respond to the start
condition and shift in the next 8 bits (7-bit address and an
R/W bit). The bits arrive MSB first. The peripheral that
recognizes the transmitted address responds by pulling the
data line low during the ninth clock pulse. This is known as the
acknowledge bit. All other devices withdraw from the bus at
this point and maintain an idle condition. An exception to this
is the general call address, which is described in the General
Call section. The idle condition is where the device monitors
the SDA and SCL lines waiting for the start condition and the
correct address byte. The R/W bit determines the direction of
the data transfer. A Logic 0 LSB in the start byte means that the
master writes information to the addressed peripheral. In this
case, the device becomes a slave receiver. A Logic 1 LSB in the
start byte means that the master reads information from the
addressed peripheral. In this case, the device becomes a slave
transmitter. In all instances, the AD7152/AD7153 act as a
standard slave device on the I2C bus.
The start byte address is Address 0x90 for a write and
Address 0x91 for a read.
WRITE OPERATION
When a write is selected, the byte following the start byte is
always the register address pointer (subaddress) byte, which
points to one of the internal registers on the AD7152/AD7153.
The address pointer byte is automatically loaded into the
address pointer register and acknowledged by the AD7152/
AD7153. After the address pointer byte acknowledge, a stop
condition, a repeated start condition, or another data byte can
follow from the master.
AD7152/AD7153
A stop condition is defined by a low-to-high transition on SDA
while SCL remains high. If a stop condition is ever encountered
by the AD7152/AD7153, it returns to its idle condition and the
address pointer is reset to Address 0x00.
If a data byte is transmitted after the register address pointer
byte, the AD7152/AD7153 load this byte into the register that
is currently addressed by the address pointer register. The devices
send an acknowledge and the address pointer autoincrementer
automatically increments the address pointer register to the
next internal register address. Thus, subsequent transmitted
data bytes are loaded into sequentially incremented addresses.
If a repeated start condition is encountered after the address
pointer byte, all peripherals connected to the bus respond
exactly as previously outlined for a start condition, that is, a
repeated start condition is treated the same as a start condition.
When a master device issues a stop condition, it relinquishes
control of the bus, allowing another master device to take
control. Hence, a master wanting to retain control of the bus
issues successive start conditions known as repeated start
conditions.
READ OPERATION
When a read is selected in the start byte, the register that is
currently addressed by the address pointer is transmitted onto
the SDA line by the AD7152/AD7153. The regulator is then
clocked out by the master device, and the AD7152/AD7153
await an acknowledge from the master.
If an acknowledge is received from the master, the address
autoincrementer automatically increments the address pointer
register and outputs the next addressed register content onto
the SDA line for transmission to the master. If no acknowledge
is received, the AD7152/AD7153 return to the idle state and the
address pointer is not incremented.
The autoincrementer of the address pointers allows block data
to be written or read from the starting address and subsequent
incremental addresses.
In continuous conversion mode, the autoincrementer of the
address pointers should be used for reading a conversion result;
that is, the three data bytes should be read using one multibyte
read transaction rather than three separate single-byte
transactions. The single-byte data read transaction may result in
the data bytes from two different results being mixed.
Rev. A | Page 11 of 24
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet AD7153.PDF ] | |
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