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N01S830BA 데이터시트 PDF




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부품번호 N01S830BA 기능
기능 1 Mb Ultra-Low Power Serial SRAM
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N01S830BA 데이터시트, 핀배열, 회로
N01S830HA, N01S830BA
1 Mb Ultra-Low Power
Serial SRAM
Standard SPI Interface and Multiplex
DUAL and QUAD Interface
Overview
The ON Semiconductor serial SRAM family includes several
integrated memory devices including this 1 Mb serially accessed
Static Random Access Memory, internally organized as 128 K words
by 8 bits. The devices are designed and fabricated using
ON Semiconductor’s advanced CMOS technology to provide both
high-speed performance and low power. The devices operate with a
single chip select (CS) input and use a simple Serial Peripheral
Interface (SPI) protocol. In SPI mode, a single data-in (SI) and
data-out (SO) line is used along with the clock (SCK) to access data
within the device. In DUAL mode, two multiplexed data-in/data-out
(SIO0-SIO1) lines are used and in QUAD mode, four multiplexed
data-in/data-out (SIO0-SIO3) lines are used with the clock to access
the memory. The devices can operate over a wide temperature range of
−40°C to +85°C (+125°C for E−Temp) and are available in a 8-lead
TSSOP package. The N01S830xA device has two different variations,
a HOLD version that allows communication to the device to be paused
and a battery back-up (BBU) version to be used with a battery to retain
data when power is lost.
Features
Power Supply Range: 2.5 to 5.5 V
Very Low Typical Standby Current < 4 mA at +85°C
Very Low Operating Current < 10 mA
Simple Serial Interface
Single-bit SPI Access
DUAL-bit and QUAD-bit SPI-like Access
Flexible Operating Modes
Word Mode
Page Mode
Burst Mode (Full Array)
High Frequency Read and Write Operation
Clock Frequency up to 20 MHz
Functional Options
HOLD Pin for Pausing Operation
VBAT Pin for Battery−Back up
Built-in Write Protection (CS High)
High Reliability
Unlimited Write Cycles
Temperature Ranges Supported
Industrial (I): TA = −40°C to +85°C
Automotive (E): TA = −40°C to +125°C
These Devices are Pb−Free and are RoHS Compliant
Green TSSOP
www.onsemi.com
TSSOP8 3x4.4
CASE 948BH
PACKAGE CONFIGURATION
CS
SO / SIO1
NC / SIO2
VSS
18
27
36
45
HOLD Version
VCC
HOLD / SIO3
SCK
SI / SIO0
CS
SO / SIO1
NC
VSS
18
27
36
45
BBU Version
VCC
VBAT
SCK
SI / SIO0
ORDERING INFORMATION
Device
Package
Shipping
N01S830HAT22I
N01S830BAT22I
N01S830HAT22IT
N01S830BAT22IT
TSSOP−8
(Pb−Free)
100 Units / Tube
TSSOP−8
(Pb−Free)
3000 / Tape
& Reel
N01S830HAT22E
N01S830BAT22E
TSSOP−8
(Pb−Free)
100 Units / Tube
N01S830HAT22ET TSSOP−8
N01S830BAT22ET (Pb−Free)
3000 / Tape
& Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
© Semiconductor Components Industries, LLC, 2016
February, 2016 − Rev. 2
1
Publication Order Number:
N01S830HA/D




N01S830BA pdf, 반도체, 판매, 대치품
N01S830HA, N01S830BA
DEVICE OPERATIONS
Read Operation
The serial SRAM Read operation is started by by enabling
CS low. First, the 8-bit Read instruction is transmitted to the
device through the SI (or SIO0-3) pin(s) followed by the
24-bit address with the 7 MSBs of the address being “don’t
care” bits and ignored. In SPI mode, after the READ
instruction and address bits are sent, the data stored at that
address in memory is shifted out on the SO pin after the
output valid time. Additional “dummy” clock cycles (four in
DUAL and two in QUAD) are required to follow the
instruction and address inputs prior to the data being driven
out on the SIO0-3 pins while operating in these two modes.
CS
By continuing to provide clock cycles to the device, data
can continue to be read out of the memory array in
sequentially. The internal address pointer is automatically
incremented to the next higher address after each byte of
data is read out until the highest memory address is reached.
When the highest memory address is reached, 1FFFFh, the
address pointer wraps to the address 00000h. This allows the
read cycles to be continued indefinitely. All Read operations
are terminated by pulling CS high.
SCK 0 1 2 3 4 5 6 7 8 9 10 11 29 30 31 32 33 34 35 36 37 38 39
Instruction
24−bit address
SI 0 0 0 0 0 0 1 1 23 22 21 20 2 1 0
SO High−Z
Data Out
76543210
Figure 2. SPI Read Sequence (Single Byte)
CS
SCK 0 1 2 3 4 5 6 7 8 9 10 11 29 30 31 32 33 34 35 36 37 38 39
Instruction
24−bit address
SI 0 0 0 0 0 0 1 1 23 22 21 20 2 1 0
Don’t Care
ADDR 1
Data Out from ADDR 1
SO High−Z
76543210
40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
Don’t Care
Data Out from ADDR 2
Data Out from ADDR 3
Data Out from ADDR n
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0 ... 7 6 5 4 3 2 1 0
Figure 3. SPI Read Sequence (Sequential Bytes)
www.onsemi.com
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N01S830BA 전자부품, 판매, 대치품
N01S830HA, N01S830BA
CS
SCK
0 1 2 3 4 5 6 7 8 9 10 11 12 13
Instruction
24−bit address
Data in
SIO[3:0]
C1 C0 A5 A4 A3 A2 A1 A0 H0 L0 H1 L1 H2 L2
MSB
MSB
Notes:
C[1:0] = 02h
H0 = 4 high order bits of data byte 0
L0 = 4 low order bits of data byte 0
H1 = 4 high order bits of data byte 1
L1 = 4 low order bits of data byte 1
Figure 8. QUAD Write Sequence
Hn Ln
READ Mode Register (RDMR)
This instruction provides the ability to read the mode
register. The register may be read at any time including
during a Write operation. The Read Mode Register
operation is executed by driving CS low, then sending the
CS
RDMR instruction to the device. Immediately after the
instruction, the device outputs data on the SO (SIO0-3)
pin(s). To complete the operation, drive CS high to terminate
the register read.
SCK
SI
SO
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
Instruction
00000101
Mode Register Data Out
High−Z
76543210
Figure 9. SPI Read Mode Register Sequence (RDMR)
CS
SCK
01234567
SIO[1:0]
Instruction
Mode Bits
C3 C2 C1 C0 H H L
L
Notes: C[3:0] = 05h
MSB
Figure 10. DUAL Read Mode Register Sequence (RDMR)
www.onsemi.com
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관련 데이터시트

부품번호상세설명 및 기능제조사
N01S830BA

1 Mb Ultra-Low Power Serial SRAM

ON Semiconductor
ON Semiconductor

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