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N34C04 데이터시트 PDF




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부품번호 N34C04 기능
기능 4-Kb Serial SPD EEPROM
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N34C04 데이터시트, 핀배열, 회로
N34C04
4-Kb Serial SPD EEPROM
for DDR4 DIMM
Description
The N34C04 is a 4−Kb serial EEPROM, which implements the
JEDEC JC42.4 (EE1004−v) Serial Presence Detect (SPD)
specification for DDR4 DIMMs and supports the Standard (100 kHz),
Fast (400 kHz) and Fast Plus (1 MHz) I2C protocols.
One of the two available 2−Kb EEPROM banks (referred to as SPD
pages in the EE1004−v specification) is activated for access at
power−up. After power−up, banks can be switched via software
command. Each of the four 1−Kb EEPROM blocks can be Write
Protected by software command.
Features
JEDEC JC42.4 (EE1004−v) Serial Presence Detect (SPD) Compliant
Temperature Range: −40°C to +125°C
Supply Range: 1.7 V − 3.6 V
I2C / SMBus Interface
Schmitt Triggers and Noise Suppression Filters on SCL and SDA
Inputs
16−Byte Page Write Buffer
Hardware Write Protection for Entire Memory
Low Power CMOS Technology
2 x 3 x 0.5 mm UDFN Package
These Devices are Pb−Free and are RoHS Compliant
VCC
SCL
A2, A1, A0
WP
N34C04
SDA
VSS
Figure 1. Functional Symbol
www.onsemi.com
1
UDFN8
MU3 SUFFIX
CASE 517AZ
PIN CONFIGURATION
A0 1
A1
(Top View)
A2
VSS
VCC
WP
SCL
SDA
UDFN (HU4)
For the location of Pin 1, please consult the
corresponding package drawing.
MARKING DIAGRAM
D2U
AZZ
YM
G
UDFN8
D2U
A
ZZ
Y
M
G
= Specific Device Code
= Assembly Location Code
= Assembly Lot Number (Last Two Digits)
= Production Year (Last Digit)
= Production Month (1 − 9, O, N, D)
= Pb−Free Package
PIN FUNCTIONS
Pin Name
Function
A0, A1, A2
SDA
SCL
WP
Device Address Input
Serial Data Input/Output
Serial Clock Input
Write Protect Input
VCC
VSS
DAP
Power Supply
Ground
Backside Exposed DAP at VSS
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 11 of this data sheet.
© Semiconductor Components Industries, LLC, 2016
November, 2016 − Rev. 0
1
Publication Order Number:
N34C04/D




N34C04 pdf, 반도체, 판매, 대치품
N34C04
Table 8. INPUT IMPEDANCE
Symbol
Parameter
ZIL Input Impedance for A0, A1, A2, WP Pins
ZIH Input Impedance for A0, A1, A2, WP Pins
Pin Description
SCL: The Serial Clock input pin accepts the Serial Clock
generated by the Master (Host).
SDA: The Serial Data I/O pin receives input data and transmits
data stored in the memory. In transmit mode, this pin is open
drain. Data is acquired on the positive edge, and is delivered
on the negative edge of SCL.
A0, A1 and A2: The Address pins accept the device address.
These pins have on−chip pull−down resistors.
WP: The Write Protect input pin inhibits all write
operations, when pulled HIGH. This pin has an on−chip
pull−down resistor. The Write Protect pin should be tied
directly either to Vcc or GND.
Power−On Reset (POR)
The N34C04 incorporates Power−On Reset (POR)
circuitry which protects the device against powering up to an
undetermined logic state. As VCC exceeds the POR trigger
level, the device will power up into standby mode. The
device will power down into Reset mode when VCC drops
below the POR trigger level. This bi−directional POR
behavior protects the N34C04 against brown−out failure
following a temporary loss of power. The POR trigger level
is set below the minimum operating VCC level.
Device Interface
The N34C04 supports the Inter−Integrated Circuit (I2C)
and the System Management Bus (SMBus) data
transmission protocols. These protocols describe serial
communication between transmitters and receivers sharing a
2−wire data bus. Data flow is controlled by a Master device,
which generates the serial clock and the START and STOP
conditions. The N34C04 acts as a Slave device. Master and
Slave alternate as transmitter and receiver. Up to 8 N34C04
devices may be present on the bus simultaneously, and can be
individually addressed by matching the logic state of the
address inputs A0, A1, and A2.
I2C/SMBus Protocol
The I2C/SMBus uses two ‘wires’, one for clock (SCL) and
one for data (SDA). The two wires are connected to the VCC
Test Conditions
VIN < 0.3 * Vcc
VIN > 0.7 * Vcc
Min Max Unit
30 kW
800 kW
supply via pull−up resistors. Master and Slave devices
connect to the bus via their respective SCL and SDA pins.
The transmitting device pulls down the SDA line to
‘transmit’ a ‘0’ and releases it to ‘transmit’ a ‘1’.
Data transfer may be initiated only when the bus is not
busy (see A.C. Characteristics).
During data transfer, the SDA line must remain stable
while the SCL line is HIGH. An SDA transition while SCL
is HIGH will be interpreted as a START or STOP condition
(Figure 2).
START
The START condition precedes all commands. It consists
of a HIGH to LOW transition on SDA while SCL is HIGH.
The START acts as a ‘wake−up’ call to all Slaves. Absent a
START, a Slave will not respond to commands.
STOP
The STOP condition completes all commands. It consists
of a LOW to HIGH transition on SDA while SCL is HIGH.
The STOP tells the Slave that no more data will be written
to or read from the Slave.
Device Addressing
The Master initiates data transfer by creating a START
condition on the bus. The Master then broadcasts an 8−bit
serial Slave address. The first 4 bits of the Slave address (the
preamble) determine whether the command is a read/write
command (1010b) or a utility command (0110b), as
described in Table 9. The next 3 bits, A2, A1 and A0, select
one of 8 possible Slave devices. The last bit, R/W, specifies
whether a Read (1) or Write (0) operation is being performed.
Acknowledge
A matching Slave address is acknowledged (ACK) by the
Slave by pulling down the SDA line during the 9th clock
cycle (Figure 3). After that, the Slave will acknowledge all
data bytes sent to the bus by the Master. When the Slave is
the transmitter, the Master will in turn acknowledge data
bytes in the 9th clock cycle. The Slave will stop transmitting
after the Master does not respond with acknowledge
(NoACK) and then issues a STOP. Bus timing is illustrated
in Figure 4.
SDA
SCL
START BIT
Figure 2. Start/Stop Timing
STOP BIT
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N34C04 전자부품, 판매, 대치품
N34C04
SCL
SDA
8th Bit
Byte n
ACK
tWR
STOP
CONDITION
Figure 6. EEPROM Write Cycle Timing
START
CONDITION
ADDRESS
BUS ACTIVITY:
MASTER
S
T
A
R
T
SDA LINE S
SLAVE
SLAVE
ADDRESS
BYTE
ADDRESS (n)
DATA n
DATA n+1
AAA
CCC
KKK
NOTE: In this example n = XXXX 0000(B); X = 1 or 0
Figure 7. EEPROM Page Write
A
C
K
DATA n+P
S
T
O
P
P
A
C
K
ADDRESS
BYTE
DATA
BYTE
1
SCL
891
8
SDA
a7
WP
a0
tSU:WP
d7
tHD:WP
Figure 8. WP Timing
d0
BUS ACTIVITY:
MASTER
S
T
A
R
T
SLAVE
ADDRESS
N
OS
AT
CO
KP
SDA LINE S
P
SLAVE
A
C DATA
K
Figure 9. EEPROM Immediate Read
www.onsemi.com
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N34C04

4-Kb Serial SPD EEPROM

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