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PDF N84C163 Data sheet ( Hoja de datos )
| Número de pieza | N84C163 | |
| Descripción | Supervisory Circuits | |
| Fabricantes | ON Semiconductor | |
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N84C163
Product Preview
Supervisory Circuits with
I2C Serial CMOS EEPROM,
Precision Reset Controller
and Watchdog Timer (16K)
www.onsemi.com
Description
The N84C163 is a complete memory and supervisory solution for
microcontroller−based systems. A serial EEPROM memory (16K)
with hardware memory write protection, a system power supervisor
with brown out protection and a watchdog timer are integrated
together in low power CMOS technology. Memory interface is via an
I2C bus.
SOIC−8
CASE 751BD
The 1.6−second watchdog circuit returns a system to a known good
state if a software or hardware glitch halts or “hangs” the system. The
N84C163 watchdog monitors the WDI input pin.
The power supply monitor and reset circuit protects memory and
PIN CONFIGURATION
SOIC 8 Lead
system controllers during power up/down and against brownout
conditions. Five reset threshold voltages support 5 V, 3.3 V and 3 V
systems. If power supply voltages are out of tolerance reset signals
become active, preventing the system microcontroller, ASIC or
WDI
RESET
WP
18
27
N84C163
36
VCC
RESET
SCL
peripherals from operating. Reset signals become inactive typically
200 ms after the supply voltage exceeds the reset threshold level. With
GND 4
5 SDA
both active high and low reset signals, interface to microcontrollers
and other ICs is simple. In addition, a reset pin can be used as a
debounced input for pushbutton manual reset capability.
The N84C163 memory features a 16−byte page. In addition,
PIN FUNCTIONS
Pin Name Function
hardware data protection is provided by a write protect pin WP and by
WDI Watchdog Timer Input
a VCC sense circuit that prevents writes to memory whenever VCC falls
below the reset threshold or until VCC reaches the reset threshold
during power up.
This device is available in a green SOIC−8 package.
RESET
WP
GND
SDA
Active Low Reset I/O
Write Protect
Ground
Serial Data/Address
Features
• Watchdog Timer Input (WDI)
• 400 kHz I2C Bus Compatible
• 2.7 V to 6.0 V Operation
SCL
RESET
VCC
Clock Input
Active High Reset I/O
Power Supply
• Low Power CMOS Technology
• 16−Byte Page Write Buffer
ORDERING INFORMATION
• Built−in Inadvertent Write Protection
For Ordering Information details, see page 10.
♦ VCC Lock Out
♦ Write Protection Pin, WP
• Active High or Low Reset
♦ Precision Power Supply Voltage Monitor
• 100 Year Data Retention
• 8−Pin SOIC Package
♦ 5 V, 3.3 V and 3 V Systems
♦ Five Threshold Voltage Options
• 1,000,000 Program/Erase Cycles
• Manual Reset
• Commercial and Industrial Temperature Ranges
• These Devices are Pb−Free, Halogen Free/BFR Free
and are RoHS Compliant
This document contains information on a product under development. ON Semiconductor
reserves the right to change or discontinue this product without notice.
© Semiconductor Components Industries, LLC, 2016
September, 2016 − Rev. P0
1
Publication Order Number:
N84C163/D
1 page  
N84C163
PIN DESCRIPTION
WDI: WATCHDOG INPUT
If there is no transition on the WDI for more than
1.6 seconds, the watchdog timer times out.
WP: WRITE PROTECT
If the pin is tied to VCC the entire memory array becomes
Write Protected (READ only). When the pin is tied to GND
or left floating normal read/write operations are allowed to
the device.
RESET/RESET: RESET I/O
These are open drain pins and can be used as reset trigger
inputs. By forcing a reset condition on the pins the device
will initiate and maintain a reset condition. The RESET pin
must be connected through a pulldown resistor, and the
RESET pin must be connected through a pull−up resistor.
SDA: SERIAL DATA ADDRESS
The bidirectional serial data/address pin is used to transfer
all data into and out of the device. The SDA pin is an open
drain output and can be wire−ORed with other open drain or
open collector outputs.
SCL: Serial Clock
Serial clock input.
DEVICE OPERATION
Reset Controller Description
The N84C163 precision RESET controller ensures
correct system operation during brownout and power
up/down conditions. It is configured with open drain
RESET outputs. During power−up, the RESET outputs
remain active until VCC reaches the VTH threshold and will
continue driving the outputs for approximately 200 ms
(tPURST) after reaching VTH. After the tPURST timeout
interval, the device will cease to drive the reset outputs. At
this point the reset outputs will be pulled up or down by their
respective pull up/down resistors. During power−down, the
RESET outputs will be active when VCC falls below VTH.
The RESET outputs will be valid so long as VCC is > 1.0 V
(VRVALID).
The RESET pins are I/Os; therefore, the N84C163 can act
as a signal conditioning circuit for an externally applied
manual reset. The inputs are edge triggered; that is, the
RESET input in the N84C163 will initiate a reset timeout
after detecting a low to high transition and the RESET input
in the N84C163 will initiate a reset timeout after detecting
a high to low transition.
Watchdog Timer
The Watchdog Timer provides an independent protection
for microcontrollers. During a system failure, the N84C163
will respond with a reset signal after a time−out interval of
1.6 seconds for a lack of activity. The N84C163 is designed
with the Watchdog Timer feature on the WDI input. If the
microcontroller does not toggle the WDI input pin within 1.6
seconds, the Watchdog Timer times out. This will generate
a reset condition on reset outputs. The Watchdog Timer is
cleared by any transition on WDI.
As long as the reset signal is asserted, the Watchdog Timer
will not count and will stay cleared.
t
GLITCH
VTH
VRVA LI D
VCC
t PURS T
t RPD
t PURS T
RESET
t RPD
RESET
Figure 1. RESET Output Timing
www.onsemi.com
5
5 Page 
PIN # 1
IDENTIFICATION
TOP VIEW
N84C163
SOIC 8, 150 mils
CASE 751BD−01
ISSUE O
E1 E
SYMBOL
A
A1
b
c
D
E
E1
e
h
L
θ
MIN
1.35
0.10
0.33
0.19
4.80
5.80
3.80
0.25
0.40
0º
NOM
1.27 BSC
MAX
1.75
0.25
0.51
0.25
5.00
6.20
4.00
0.50
1.27
8º
D
A1
A
eb
SIDE VIEW
Notes:
(1) All dimensions are in millimeters. Angles in degrees.
(2) Complies with JEDEC MS-012.
h
θ
L
END VIEW
c
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N84C163/D
11
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| Páginas | Total 11 Páginas | |
| PDF Descargar | [ Datasheet N84C163.PDF ] | |
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