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PDF BU8254KVT Data sheet ( Hoja de datos )
| Número de pieza | BU8254KVT | |
| Descripción | 35bit LVDS Transmitter | |
| Fabricantes | ROHM Semiconductor | |
| Logotipo |  |
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LVDS Interface ICs
35bit LVDS Transmitter
35:5 Serializer
BU8254KVT
No.13057ECT06
●Description
LVDS Interface IC of ROHM "Serializer" "Deserializer" operate from 8MHz to 150MHz wide clock range, and number of bits
range is from 35 to 70. Data is transmitted seven times (7X) stream and reduce cable number by 3(1/3) or less. The
ROHM's LVDS has low swing mode to be able to expect further low EMI.
●Features
1) 35bits data of parallel LVCMOS level inputs are converted to five channels of LVDS data stream.
2) 30bits of RGB data and 5bits of timing and control data(HSYNC,VSYNC,DE,CNTL1,CNTL2) are transmitted up to
784Mbps effective rate per LVDS channel.
3) Support clock frequency from 8MHz up to 112MHz.
4) Support consumer video format including 480i, 480P, 720P and 1080i as well.
5) Clock edge selectable
6) Power down mode
7) Support spread spectrum clock generator.
8) Support reduced swing LVDS for low EMI.
9) 30bit LVDS receiver is recommended to use BU90R104.
●Applications
Flat Panel Display
●Precaution
■This chip is not designed to protect from radioactivity.
■The chip is made strictly for the specific application or equipment.
Then it is necessary that the unit is measured as need.
■This document may be used as strategic technical data which subjects to COCOM regulations.
www.rohm.com
© 2013 ROHM Co., Ltd. All rights reserved.
1/17
2013.06 - Rev.C
1 page  
BU8254KVT
●Pin Description
Technical Note
Table 1 : Pin Description
Pin Name
Pin No.
TAP, TAN
30,31
TBP, TBN
28,29
TCP, TCN
24,25
TDP, TDN
20,21
TEP, TEN
18,19
TCLKP, TCLKN
22,23
TA0～TA6
33,34,35,36,37,38,40
TB0～TB6
41,42,44,45,46,48,49
TC0～TC6
50,52,53,54,55,57,58
TD0～TD6
59,61,62,63,64,1,3
TE0～TE6
4,5,6,8,9,11,16
XRST
13
RS 43
RF
VDD
CLKIN
GND
LVDS VDD
LVDS GND
PLLVDD
PLLGND
60
51,7
12
2,10,39,47,56
27
17,26,32
15
14
Type
Descriptions
LVDS OUT
LVDS OUT
LVDS OUT LVDS data out.
LVDS OUT
LVDS OUT
LVDS OUT LVDS clock out.
IN
IN
IN Pixel data inputs.
IN
IN
IN
IN
IN
Power
H : Normal operation,
L : Power down (all outputs are Hi-Z)
LVDS swing mode, VREF *1select.
RS LVDS Swing
VDD
0.6～1.4V
350mV
350mV
GND
200mV
*1 VREF is Input Reference Voltage.
Small Swing
Input Support
N/A
RS-VREF
N/A
Input clock triggering edge select.
H : Rising edge, L : Falling edge.
Power supply pins for LVCMOS inputs and digital core.
IN Clock input.
Ground Ground pins for LVCMOS inputs and digital core.
Power
Power supply pins for LVDS outputs.
Ground Ground pins for LVDS outputs.
Power
Power supply pin for PLL core.
Ground Ground pins for PLL core.
www.rohm.com
© 2013 ROHM Co., Ltd. All rights reserved.
5/17
2013.06 - Rev.C
5 Page 
BU8254KVT
●AC Timing
■AC Timing Diagrams
LVCMOS Input
LVCMOS Output
LVDS Output
Vdiff=(TAP)-(TAN)
TAP
TAN
LVDS Output Load
90%
CLKIN
10%
tTCIT
80%
RL Vdiff 20%
tLVT
Technical Note
90%
10%
tTCIT
80%
20%
tLVT
LVCMOS Input
CLKIN VDD/2
tTCP
tTCH
VDD/2
tTS
tTCL
tTH
VDD/2
Tx0-Tx6
VDD/2
VDD/2
TCLKP
TCLKN
tTCD
RF=L
RF=H
VOC
Fig.6 AC Timing Diagrams
www.rohm.com
© 2013 ROHM Co., Ltd. All rights reserved.
11/17
2013.06 - Rev.C
11 Page | ||
| Páginas | Total 21 Páginas | |
| PDF Descargar | [ Datasheet BU8254KVT.PDF ] | |
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