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부품번호 | BU97500KV 기능 |
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기능 | Multifunction LCD Segment Driver | ||
제조업체 | ROHM Semiconductor | ||
로고 | |||
전체 26 페이지수
Datasheet
Multifunction LCD Segment Driver
BU97500KV MAX 204 segments (SEG51×COM4)
●Features
Integrated RAM for display data (DDRAM):
51 x 4bit (Max 204 Segment)
LCD drive output:
4 Common output, Max 51Segment output
Segment/GPO (Max 4port) output mode selectable
Support standby mode
Integrated Power-on Reset circuit
Integrated Oscillator circuit
No external component
Low power consumption design
Independent power supply for LCD driving
●Applications
Telephone
FAX
Portable equipment (POS, ECR, PDA etc.)
DSC
DVC
Car audio
Home electrical appliance
Meter equipment
etc.
●Key Specifications
■ Supply Voltage Range:
+2.7V to +5.5V
■ LCD drive power supply Range: +4.5V to +5.5V
■ Operating Temperature Range: -40°C to +85°C
■ Max Segments:
204 Segments
■ Display Duty:
1/3, 1/4 selectable
■ Bias:
1/2, 1/3 selectable
■ Interface:
3wire serial interface
●Package
W (Typ.) x D (Typ.) x H (Max.)
VQFP64
12.00mm x 12.00mm x 1.60mm
●Typical Application Circuit
+5V
+5.5V
*1
*1
VDD
VLCD
From
Control
RESB
CSB
SCL
SD
OPEN DO
OSC
COM1
COM2
COM3
P1/S1
P2/S2
(P1)
(P2) (General purpose ports)
(For use control of backlight)
(P4)
P4/S4
S5
S40
COM4/S41
S42
S52
LCD Panel
(Up to 204
Segments)
*1 Insert capacitors between VDD and VSS
C≥0.1uF
Figure 1. Typical application circuit
○Product structure:Silicon monolithic integrated circuit
www.rohm.com
© 2013 ROHM Co., Ltd. All rights reserved.
TSZ22111・14・001
○This product is not designed for protection against radioactive rays.
1/23
TSZ02201-0A0A2D300050-1-2
8.Jan.2013 Rev.002
BU97500KV MAX 204 segments (SEG51×COM4)
Datasheet
●Electrical Characteristics – continued
Oscillation Characteristics (Ta=-40°C to +85°C, VDD=2.7 to 5.5V, VLCD=4.5V to 5.5V, VSS=0V)
Parameters
Symbol
MIN
Limits
TYP
MAX
Unit
Condition
Frame Frequency
fFR 56 80 104 Hz fFR = 80Hz setting, 1/4 Duty setting
MPU interface Characteristics (Ta=-40 to +85°C, VDD=2.7V to 5.5V, VLCD=4.5 to 5.5V, VSS=0V)
Parameters
Symbol
MIN.
Limits
TYP.
MAX.
Unit
Condition
Input Rise Time
tr - - 80 ns
Input Fall Time
tf - - 80 ns
SCL Cycle Time
tSCYC 400
-
- ns
“H” SCL Pulse Width
tSHW
100
-
- ns
“L” SCL Pulse Width
tSLW
100
-
- ns
SD Setup Time
tSDS
20
-
- ns
SD Hold Time
tSDH
20
-
- ns
CSB Setup Time
tCSS
50
-
- ns
CSB Hold Time
tCSH
50
-
- ns
“H” CSB Pulse Time
tCHW
50
-
- ns
CSB
SCL
tCSS
tf
tSLW
tSCYC
tSHW
tr
tCSH
tCHW
tSDS tSDH
SD
Figure 4. Serial interface Timing
Reset Timing characteristics (Ta=-40 to +85°C, VDD=2.7V to 5.5V, VLCD=4.5 to 5.5V, VSS=0V)
Limits
Item Symbol
Unit
MIN.
TYP.
MAX.
Input Rise Time
tr -
- 80 ns
Input Fall Time
tf -
- 80 ns
Reset Pulse Width tRW 3 - - us
Reset Release Time
tRT
1
-
- ms
Condition
www.rohm.com
© 2013 ROHM Co., Ltd. All rights reserved.
TSZ22111・15・001
Figure 5. Reset Timing
4/23
TSZ02201-0A0A2D300050-1-2
8.Jan.2013 Rev.002
4페이지 BU97500KV MAX 204 segments (SEG51×COM4)
Datasheet
○Display data transfer method
This LSI has Display Data RAM (DDRAM) of 51×4=204bit.
The relationship between data input and display data, DDRAM data and address are as follows.
Command
00001010 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 …
→ Display Data
The address to be written is the address specified by ADSET command, and the address is automatically incremented in
every 4bit data if 1/4 Duty mode or in every 3 bit if 1/3 Duty mode respectively.
(1)1/3 Duty Mode
DDRAM Address/Segment Outputs
00h 01h 02h 03h 04h .... 31h 32h 33h
0 D0 D3 D6 D9 D12
D148 D151 D154 COM1
BIT 1 D1 D4 D7 D10 D13
D149 D152 D155 COM2
2 D2 D5 D8 D11 D14
D150 D153 D156 COM3
S1 S2 S3 S4 S5
S50 S51 S52
Transferred data is written to the DDRAM by every 3bit. The write operation is cancelled if it changes CSB=”L”→”H”
before 3bits data transfer.
(2)1/4 Duty Mode
DDRAM Address/ Segment Outputs
00h 01h 02h 03h 04h .... 30h 31h 32h
0 D0 D4 D8 D12 D16
D193 D197 D201 COM1
1
BIT
2
D1
D2
D5 D9 D13 D17
D6 D10 D14 D18
D194 D198 D202
D195 D199 D203
COM2
COM3
3 D3 D7 D11 D15 D19
D196 D200 D204 COM4
S1 S2 S3 S4 S5
S50 S51 S52
Transferred Data is written to the DDRAM by every 4bit. The write operation is cancelled if it changes CSB=”L”→”H”
before 4bits data transfer.
www.rohm.com
© 2013 ROHM Co., Ltd. All rights reserved.
TSZ22111・15・001
7/23
TSZ02201-0A0A2D300050-1-2
8.Jan.2013 Rev.002
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부품번호 | 상세설명 및 기능 | 제조사 |
BU97500KV | Multifunction LCD Segment Driver | ROHM Semiconductor |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |