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PDF 74ALVT162823 Data sheet ( Hoja de datos )
| Número de pieza | 74ALVT162823 | |
| Descripción | 18-bit bus-interface D-type flip-flop | |
| Fabricantes | Philips | |
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74ALVT162823
18-bit bus-interface D-type flip-flop with reset and enable with
30 Ω termination resistors; 3-state
Rev. 02 — 11 August 2005
Product data sheet
1. General description
The 74ALVT162823 18-bit bus interface register is designed to eliminate the extra
packages required to buffer existing registers and provide extra data width for wider data
or address paths of buses carrying parity.
The 74ALVT162823 has two 9-bit wide buffered registers with clock enable (nCE) and
master reset (nMR) which are ideal for parity bus interfacing in high microprogrammed
systems.
The registers are fully edge-triggered. The state of each D input, one set-up time before
the LOW-to-HIGH clock transition is transferred to the corresponding Q output of the
flip-flop.
The 74ALVT162823 is designed with 30 Ω series resistance in both the pull-up and
pull-down output structures. This design reduces line noise in applications such as
memory address drivers, clock drivers, and bus receivers or transmitters.
2. Features
s Two sets of high speed parallel registers with positive edge-triggered D-type flip-flops
s 5 V I/O compatible
s Ideal where high speed, light loading or increased fan-in are required with MOS
microprocessors
s Bus hold data inputs eliminate the need for external pull-up resistors to hold unused
inputs
s Live insertion and extraction permitted
s Power-up 3-state
s Power-up reset
s Output capability: +12 mA to −12 mA
s Outputs include series resistance of 30 Ω making external termination resistors
unnecessary
s Latch-up protection:
x JESD78: exceeds 500 mA
s ESD protection:
x MIL STD 883, method 3015: exceeds 2000 V
x Machine Model: exceeds 200 V
1 page  
Philips Semiconductors
74ALVT162823
18-bit bus-interface D-type flip-flop with reset and enable; 3-state
6. Pinning information
6.1 Pinning
1MR 1
1OE 2
1Q0 3
GND 4
1Q1 5
1Q2 6
VCC 7
1Q3 8
1Q4 9
1Q5 10
GND 11
1Q6 12
1Q7 13
1Q8 14
2Q0 15
2Q1 16
2Q2 17
GND 18
2Q3 19
2Q4 20
2Q5 21
VCC 22
2Q6 23
2Q7 24
GND 25
2Q8 26
2OE 27
2MR 28
Fig 5. Pin configuration
74ALVT162823
56 1CP
55 1CE
54 1D0
53 GND
52 1D1
51 1D2
50 VCC
49 1D3
48 1D4
47 1D5
46 GND
45 1D6
44 1D7
43 1D8
42 2D0
41 2D1
40 2D2
39 GND
38 2D3
37 2D4
36 2D5
35 VCC
34 2D6
33 2D7
32 GND
31 2D8
30 2CE
29 2CP
001aab433
6.2 Pin description
Table 3:
Symbol
1MR
1OE
1Q0
GND
1Q1
1Q2
VCC
1Q3
Pin description
Pin
1
2
3
4
5
6
7
8
Description
1 master reset input (active LOW)
1 output enable input (active LOW)
1 data output 0
ground (0 V)
1 data output 1
1 data output 2
supply voltage
1 data output 3
74ALVT162823_2
Product data sheet
Rev. 02 — 11 August 2005
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
5 of 20
5 Page 
Philips Semiconductors
74ALVT162823
18-bit bus-interface D-type flip-flop with reset and enable; 3-state
11. Dynamic characteristics
Table 8: Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); for test circuit see Figure 11;
Tamb = −40 °C to +85 °C.
Symbol Parameter
Conditions
Min Typ
Max Unit
VCC = 2.5 V ± 0.2 V [1]
tPLH propagation delay nCP to nQx
tPHL propagation delay
nCP to nQx
see Figure 6
see Figure 6
2.1 3.7 5.8 ns
2.0 2.8 4.6 ns
nMR to nQx
see Figure 8
2.0 3.0 4.6 ns
tPZH
tPZL
tPHZ
tPLZ
tsu(H)
output enable time to HIGH-level see Figure 9
output enable time to LOW-level see Figure 10
output disable time from HIGH-level see Figure 9
output disable time from LOW-level see Figure 10
set-up time HIGH
nDx to nCP
see Figure 7
2.8 4.4 6.6 ns
2.0 3.4 5.2 ns
2.3 3.2 4.6 ns
2.0 2.5 3.5 ns
1.0 0.5 -
ns
nCE to nCP
see Figure 7
1.0 0.2 -
ns
tsu(L)
set-up time LOW
nDx to nCP
see Figure 7
2.0 1.3 -
ns
nCE to nCP
see Figure 7
+0.5 −0.1 -
ns
th(H) hold time HIGH
nDx to nCP
see Figure 7
+0.1 −1.4 -
ns
nCE to nCP
see Figure 7
1.0 0.2 -
ns
th(L) hold time LOW
nDx to nCP
see Figure 7
+0.1 −0.5 -
ns
nCE to nCP
see Figure 7
+1.0 −0.1 -
ns
tWH pulse width HIGH nCP
tWL pulse width LOW
nCP
see Figure 6
see Figure 6
2.0 0.8 -
3.0 2.1 -
ns
ns
nMR
see Figure 8
2.0 0.8 -
ns
trec recovery time nMR to nCP
VCC = 3.3 V ± 0.3 V [2]
tPLH propagation delay nCP to nQx
tPHL propagation delay
nCP to nQx
see Figure 8
see Figure 6
see Figure 6
2.3 1.3 -
ns
1.8 2.9 4.4 ns
1.6 2.3 3.6 ns
nMR to nQx
see Figure 8
1.8 2.5 3.7 ns
tPZH output enable time to HIGH-level see Figure 9
tPZL output enable time to LOW-level see Figure 10
tPHZ output disable time from HIGH-level see Figure 9
tPLZ output disable time from LOW-level see Figure 10
2.0 3.5 5.2 ns
1.7 2.8 3.8 ns
2.4 3.5 4.7 ns
1.9 2.8 3.8 ns
74ALVT162823_2
Product data sheet
Rev. 02 — 11 August 2005
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
11 of 20
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