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PDF BU9794AKV Data sheet ( Hoja de datos )
| Número de pieza | BU9794AKV | |
| Descripción | Standard LCD Segment Driver | |
| Fabricantes | ROHM Semiconductor | |
| Logotipo |  |
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Datasheet
Standard LCD Segment Driver
BU9794AKV MAX 200 segments (SEG50×COM4)
●Features
Integrated RAM for display data (DDRAM) :
50 × 4bit (Max 200 Segment)
LCD drive output :
4 Common output, 50 Segment output
Integrated Buffer AMP for LCD driving
Integrated Oscillator circuit
No external components
Low power consumption design
Independent power supply for LCD driving
●Applications
Telephone
FAX
Portable equipment (POS, ECR, PDA etc.)
DSC
DVC
Car audio
Home electrical appliance
Meter equipment, etc.
●Key Specifications
■ Supply Voltage Range:
+2.5V to +5.5V
■ LCD drive power supply Range: +2.5V to +5.5V
■ Operating Temperature Range: -40°C to +85°C
■ Max Segments:
200 Segments
■ Display Duty:
1/4
■ Bias:
1/2, 1/3 selectable
■ Interface:
3wire serial interface
●Package
W (Typ.) x D (Typ.) x H (Max.)
VQFP64
12.00mm x 12.00mm x 1.60mm
●Typical Application Circuit
VLCD VDD
VDD
VLCD
Controller
VDD
CSB
SD
SCL
INHb
OSCIN
TEST1
TEST2
VSS
COM0
COM1
COM2
COM3
SEG0
SEG1
SEG49
Segment
LCD
Internal oscillator circuit mode
Figure 1. Typical application circuit
○Product structure：Silicon monolithic integrated circuit
www.rohm.com
© 2013 ROHM Co., Ltd. All rights reserved.
TSZ22111･14･001
○This product is not designed for protection against radioactive rays.
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1 page  
BU9794AKV MAX 200 Segments (SEG50×COM4)
●Example of recommended circuit
VLCD VDD
VDD
VLCD
Controller
VDD
CSB
SD
SCL
INHb
OSCIN
TEST1
TEST2
VSS
COM0
COM1
COM2
COM3
SEG0
SEG1
SEG49
Internal oscillator circuit mode
Segment
LCD
VLCD
VDD
VDD
VLCD
Controller
CSB
SD
SCL
VDD
INHb
OSCIN
TEST1
TEST2
VSS
COM0
COM1
COM2
COM3
SEG0
SEG1
SEG49
Segment
LCD
External clock input mode
Figure 6. Example of recommended circuit
www.rohm.com
© 2013 ROHM Co., Ltd. All rights reserved.
TSZ22111･15･001
5/22
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10.Apr.2015 Rev.004
5 Page 
BU9794AKV MAX 200 Segments (SEG50×COM4)
○Software Reset (SWRST)
MSB
LSB
D7 D6 D5 D4 D3 D2 D1 D0
C1 1 0 1 0 1 1
This command will set initial condition
○Blink Control (BLKCTL)
MSB
LSB
D7 D6 D5 D4 D3 D2 D1 D0
C 1 1 1 0 * P1 P0
(Don‟t care)
Set blink mode
Blink mode (Hz)
OFF
0.5
1
2
P1 P0 Reset initialize condition
00
○
01
10
11
○All Pixel Control (APCTL)
MSB
LSB
7 D6 D5 D4 D3 D2 D1 D0
C 1 1 1 1 1 P1 P0
All display set ON, OFF
APON
P1
Normal
0
All pixel ON
1
Reset initialize condition
○
APOFF
Normal
All pixel OFF
P0 Reset initialize condition
0○
1
All pixels ON: All pixels are ON regardless of DDRAM data
All pixels OFF: All pixels are OFF regardless of DDRAM data
(Note) This command is valid in Display on status. The data of DDRAM don‟t change by this command.
If set both P1 and P0 =“1”, APOFF will be select.
www.rohm.com
© 2013 ROHM Co., Ltd. All rights reserved.
TSZ22111･15･001
11/22
TSZ02201-0A0A2D300010-1-2
10.Apr.2015 Rev.004
11 Page | ||
| Páginas | Total 26 Páginas | |
| PDF Descargar | [ Datasheet BU9794AKV.PDF ] | |
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