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PDF MC54HC393A Data sheet ( Hoja de datos )
| Número de pieza | MC54HC393A | |
| Descripción | Dual 4-Stage Binary Ripple Counter | |
| Fabricantes | Motorola Semiconductors | |
| Logotipo |  |
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MOTOROLA
SEMICONDUCTOR TECHNICAL DATA
Product Preview
Dual 4-Stage
Binary Ripple Counter
High–Performance Silicon–Gate CMOS
The MC54/74HC393A is identical in pinout to the LS393. The device
inputs are compatible with standard CMOS outputs; with pullup resistors,
they are compatible with LSTTL outputs.
This device consists of two independent 4–bit binary ripple counters with
parallel outputs from each counter stage. A ÷ 256 counter can be obtained
by cascading the two binary counters.
Internal flip–flops are triggered by high–to–low transitions of the clock
input. Reset for the counters is asynchronous and active–high. State
changes of the Q outputs do not occur simultaneously because of internal
ripple delays. Therefore, decoded output signals are subject to decoding
spikes and should not be used as clocks or as strobes except when gated
with the Clock of the HC393A.
• Output Drive Capability: 10 LSTTL Loads
• Outputs Directly Interface to CMOS, NMOS, and TTL
• Operating Voltage Range: 2 to 6 V
• Low Input Current: 1 µA
• High Noise Immunity Characteristic of CMOS Devices
• In Compliance with the Requirements Defined by JEDEC Standard
No. 7A
• Chip Complexity: 236 FETs or 59 Equivalent Gates
MC54/74HC393A
14
1
J SUFFIX
CERAMIC PACKAGE
CASE 632–08
14
1
14
1
N SUFFIX
PLASTIC PACKAGE
CASE 646–06
D SUFFIX
SOIC PACKAGE
CASE 751A–03
14
1
DT SUFFIX
TSSOP PACKAGE
CASE 948G–01
ORDERING INFORMATION
MC54HCXXXAJ
MC74HCXXXAN
MC74HCXXXAD
MC74HCXXXADT
Ceramic
Plastic
SOIC
TSSOP
LOGIC DIAGRAM
CLOCK 1, 13
BINARY
COUNTER
RESET 2, 12
PIN 14 = VCC
PIN 7 = GND
3, 11 Q1
4, 10 Q2
5, 9 Q3
6, 8 Q4
PIN ASSIGNMENT
CLOCK a
RESET a
Q1a
Q2a
Q3a
Q4a
GND
1
2
3
4
5
6
7
14 VCC
13 CLOCK b
12 RESET b
11 Q1b
10 Q2b
9 Q3b
8 Q4b
FUNCTION TABLE
Inputs
Clock
Reset
Outputs
XH
L
H L No Change
L L No Change
L No Change
L Advance to
Next State
This document contains information on a product under development. Motorola reserves the right to change or discontinue this product without notice.
10/95
© Motorola, Inc. 1995
1 REV 0
1 page  
MC54/74HC393A
PIN DESCRIPTIONS
INPUTS
Clock (Pins 1, 13)
Clock input. The internal flip–flops are toggled and the
counter state advances on high–to–low transitions of the
clock input.
CONTROL INPUTS
Reset (Pins 2, 12)
Active–high, asynchronous reset. A separate reset is pro-
vided for each counter. A high at the Reset input prevents
counting and forces all four outputs low.
OUTPUTS
Q1, Q2, Q3, Q4 (Pins 3, 4, 5, 6, 8, 9, 10, 11)
Parallel binary outputs Q4 is the most significant bit.
CLOCK
Q
tf
90%
50%
10%
tr
90%
50%
10%
tw
1/fmax
tPLH tPHL
tTLH tTHL
Figure 1.
SWITCHING WAVEFORMS
VCC
RESET
GND
tPHL
Q
CLOCK
tw
50%
50%
trec
50%
Figure 2.
VCC
GND
VCC
GND
DEVICE
UNDER
TEST
TEST
POINT
OUTPUT
CL*
* Includes all probe and jig capacitance
Figure 3. Test Circuit
EXPANDED LOGIC DIAGRAM
CLOCK 1, 13
CQ
DQ
3, 11 Q1
CQ
DQ
4, 10 Q2
CQ
DQ
5, 9 Q3
CQ
DQ
6, 8 Q4
RESET 2, 12
High–Speed CMOS Logic Data
DL129 — Rev 6
5
MOTOROLA
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet MC54HC393A.PDF ] | |
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