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EM68B16CWQH 데이터시트 PDF




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부품번호 EM68B16CWQH 기능
기능 32M x 16 bit DDRII Synchronous DRAM
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EM68B16CWQH 데이터시트, 핀배열, 회로
EtronTech
EM68B16CWQH
32M x 16 bit DDRII Synchronous DRAM (SDRAM)
Advance (Rev. 1.6, Oct. /2015)
Features
JEDEC Standard Compliant
JEDEC standard 1.8V I/O (SSTL_18-compatible)
Power supplies: VDD & VDDQ = +1.8V ± 0.1V
Operating temperature: TC = 0~85°C
Supports JEDEC clock jitter specification
Fully synchronous operation
Fast clock rate: 333/400/533MHz
Differential Clock, CK & CK#
Bidirectional single/differential data strobe
- DQS & DQS#
4 internal banks for concurrent operation
4-bit prefetch architecture
Internal pipeline architecture
Precharge & active power down
Programmable Mode & Extended Mode registers
Posted CAS# additive latency (AL): 0, 1, 2, 3, 4, 5, 6
WRITE latency = READ latency - 1 tCK
Burst lengths: 4 or 8
Burst type: Sequential / Interleave
DLL enable/disable
Off-Chip Driver (OCD)
- Impedance Adjustment
- Adjustable data-output drive strength
On-die termination (ODT)
RoHS compliant
Auto Refresh and Self Refresh
8192 refresh cycles / 64ms
84-ball 8x12.5x1.2mm (max) FBGA
- Pb and Halogen Free
Overview
The EM68B16C is a high-speed CMOS Double-
Data-Rate-Two (DDR2), synchronous dynamic random-
access memory (SDRAM) containing 512 Mbits in a 16-
bit wide data I/Os. It is internally configured as a quad
bank DRAM, 4 banks x 8Mb addresses x 16 I/Os.
The device is designed to comply with DDR2 DRAM
key features such as posted CAS# with additive latency,
Write latency = Read latency -1, Off-Chip Driver (OCD)
impedance adjustment, and On Die Termination(ODT).
All of the control and address inputs are synchronized
with a pair of externally supplied differential clocks.
Inputs are latched at the cross point of differential clocks
(CK rising and CK# falling). All I/Os are synchronized
with a pair of bidirectional strobes (DQS and DQS#) in
a source synchronous fashion. The address bus is used
to convey row, column, and bank address information
in RAS #, CAS# multiplexing style. Accesses begin
with the registration of a Bank Activate command, and
then it is followed by a Read or Write command. Read
and write accesses to the DDR2 SDRAM are 4 or 8-bit
burst oriented; accesses start at a selected location
and continue for a programmed number of locations in
a programmed sequence. Operating the four memory
banks in an interleaved fashion allows random access
operation to occur at a higher rate than is possible with
standard DRAMs. An auto precharge function may be
enabled to provide a self-timed row precharge that is
initiated at the end of the burst sequence. A sequential
and gapless data rate is possible depending on burst
length, CAS latency, and speed grade of the device.
Table 1. Ordering Information
Part Number
Clock Frequency
EM68B16CWQH-18H*
533MHz
EM68B16CWQH-25H*
400MHz
EM68B16CWQH-3H*
333MHz
WQ: indicates 8x12.5x1.2mm (max) FBGA package
H: indicates Generation Code
H*: indicates Pb and Halogen Free
Data Rate
1066Mbps/pin
800Mbps/pin
667Mbps/pin
Power Supply
VDD 1.8V, VDDQ 1.8V
VDD 1.8V, VDDQ 1.8V
VDD 1.8V, VDDQ 1.8V
Package
FBGA
FBGA
FBGA
Etron Technology, Inc.
No. 6, Technology Rd. V, Hsinchu Science Park, Hsinchu, Taiwan 30078, R.O.C.
TEL: (886)-3-5782345 FAX: (886)-3-5778671
Etron Technology, Inc. reserves the right to change products or specification without notice.




EM68B16CWQH pdf, 반도체, 판매, 대치품
EtronTech
EM68B16CWQH
Figure 3. State Diagram
OCD
calibration
Setting
MR,
EMR(1)
EMR(2)
EMR(3)
CKEL
Active
Power
Down
WR
Writing
WRA
Writing
With
Autoprecharge
Initialization
Sequence
PR
(E)MRS
Idle
All banks
precharged
ACT
SCRKFEH
CKCEKHEL
CKEL
Activating
CKEL
Self
Refreshing
REF
Refreshing
Precharge
Power
Down
CKEL
CKEL
Automatic Sequence
Cammand Sequence
CKEH
CKEL
WR
Bank
Active
WR
WRA
RD RD
Reading
RD
RDA
RDA
PR, PRA
PR, PRA
RDA
PR, PRA
Reading
With
Autoprecharge
Precharging
CKEL = CKE LOW, enter Power Down
CKEH = CKE HIGH, exit Power Down,exit Self Refresh
ACT = Activate
WR(A) = Write (with Autoprecharge)
RD(A) = Read (with Autoprecharge)
PR(A) = Precharge (All)
(E)MRS = (Extended) Mode Register Set
SRF = Enter Self Refresh
REF = Refresh
Note: Use caution with this diagram. It is indented to provide a floorplan of the possible state transitions and the
commands to control them, not all details. In particular situations involving more than one bank,
enabling/disabling on-die termination, Power Down entry/exit, timing restrictions during state transitions, among
other things, are not captured in full detail.
Rev. 1.6
4
Oct. /2015

4페이지










EM68B16CWQH 전자부품, 판매, 대치품
EtronTech
EM68B16CWQH
Operation Mode
The following tables provide a quick reference of available DDR2 SDRAM commands, including CKE power-down
modes and bank-to-bank commands.
Table 4. Truth Table (Note (1), (2))
Command
State CKEn-1 CKEn DM BA0,1 A10 A0-9, 11-12 CS# RAS# CAS# WE#
BankActivate
Idle(3)
H
HX V
Row address L
L
H
H
Single Bank Precharge
Any H H X V L
X
L LHL
All Banks Precharge
Any H H X X H
X
L LHL
Write
Write with AutoPrecharge
Active(3)
Active(3)
H
H
H X V L Column L H L
H X V H address L H L
(A0 – A9)
L
L
Read
Read and Autoprecharge
Active(3) H H X V L Column L H L H
Active(3) H H X V H address L H L H
(A0 – A9)
(Extended) Mode Register Set Idle H H X V
OP code
LLLL
No-Operation
Any H X X X X
X
L HHH
Device Deselect
Any H X X X X
X
HXXX
Refresh
Idle H H X X X
X
L L LH
SelfRefresh Entry
Idle H L X X X
X
L L LH
SelfRefresh Exit
Idle L H X X X
X
HXXX
L HHH
Power Down Mode Entry
Idle H L X X X
X
HXXX
L HHH
Power Down Mode Exit
Any L H X X X
X
HXXX
L HHH
Data Input Mask Disable
Active H
XL X X
X
XXXX
Data Input Mask Enable(4)
Active H
XH X X
X
XXXX
NOTE 1: V=Valid data, X=Don't Care, L=Low level, H=High level
NOTE 2: CKEn signal is input level when commands are provided.
CKEn-1 signal is input level one clock cycle before the commands are provided.
NOTE 3: These are states of bank designated by BA signal.
NOTE 4: LDM and UDM can be enabled respectively.
Rev. 1.6
7
Oct. /2015

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EM68B16CWQH

32M x 16 bit DDRII Synchronous DRAM

Etron Technology
Etron Technology

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