Datasheet.kr   

EM68C16CWQE 데이터시트 PDF




Etron Technology에서 제조한 전자 부품 EM68C16CWQE은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


 

PDF 형식의 EM68C16CWQE 자료 제공

부품번호 EM68C16CWQE 기능
기능 64M x 16 bit DDRII Synchronous DRAM
제조업체 Etron Technology
로고 Etron Technology 로고


EM68C16CWQE 데이터시트 를 다운로드하여 반도체의 전기적 특성과 매개변수에 대해 알아보세요.




전체 30 페이지수

미리보기를 사용할 수 없습니다

EM68C16CWQE 데이터시트, 핀배열, 회로
EtronTech
EM68C16CWQE
64M x 16 bit DDRII Synchronous DRAM (SDRAM)
Advance (Rev. 1.6, May /2016)
Features
JEDEC Standard Compliant
JEDEC standard 1.8V I/O (SSTL_18-compatible)
Power supplies: VDD & VDDQ = +1.8V 0.1V
Operating temperature: TC = 0~85°C
Supports JEDEC clock jitter specification
Fully synchronous operation
Fast clock rate: 333/400/533 MHz
Differential Clock, CK & CK#
Bidirectional single/differential data strobe
- DQS & DQS#
8 internal banks for concurrent operation
4-bit prefetch architecture
Internal pipeline architecture
Precharge & active power down
Programmable Mode & Extended Mode registers
Posted CAS# additive latency (AL): 0, 1, 2, 3, 4, 5, 6
WRITE latency = READ latency - 1 tCK
Burst lengths: 4 or 8
Burst type: Sequential / Interleave
DLL enable/disable
Off-Chip Driver (OCD)
- Impedance Adjustment
- Adjustable data-output drive strength
On-die termination (ODT)
RoHS compliant
Auto Refresh and Self Refresh
8192 refresh cycles / 64ms
84-ball 8 x 12.5 x 1.2mm (max) FBGA package
- Pb and Halogen Free
Overview
The EM68C16C is a high-speed CMOS Double-
Data-Rate-Two (DDR2), synchronous dynamic random
- access memory (SDRAM) containing 1024 Mbits in a
16-bit wide data I/Os. It is internally configured as a 8-
bank DRAM, 8 banks x 8Mb addresses x 16 I/Os. The
device is designed to comply with DDR2 DRAM key
features such as posted CAS# with additive latency,
Write latency = Read latency -1, Off-Chip Driver (OCD)
impedance adjustment, and On Die Termination(ODT).
All of the control and address inputs are synchronized
with a pair of externally supplied differential clocks.
Inputs are latched at the cross point of differential clocks
(CK rising and CK# falling). All I/Os are synchronized
with a pair of bidirectional strobes (DQS and DQS#) in
a source synchronous fashion. The address bus is used
to convey row, column, and bank address information
in RAS #, CAS# multiplexing style. Accesses begin with
the registration of a Bank Activate command, and then
it is followed by a Read or Write command. Read and
write accesses to the DDR2 SDRAM are 4 or 8-bit burst
oriented; accesses start at a selected location and
continue for a programmed number of locations in a
programmed sequence. Operating the eight memory
banks in an interleaved fashion allows random access
operation to occur at a higher rate than is possible with
standard DRAMs. An auto precharge function may be
enabled to provide a self-timed row precharge that is
initiated at the end of the burst sequence. A sequential
and gapless data rate is possible depending on burst
length, CAS latency, and speed grade of the device.
Table 1. Ordering Information
Part Number
Clock Frequency Data Rate
EM68C16CWQE-18H
533MHz
1066Mbps/pin
EM68C16CWQE-25H
400MHz
800Mbps/pin
EM68C16CWQE-3H
333MHz
667Mbps/pin
WQ: indicates 8 x 12.5 x 1.2mm FBGA Package
E: indicates Generation Code
H: indicates Pb and Halogen Free
Power Supply
VDD 1.8V, VDDQ 1.8V
VDD 1.8V, VDDQ 1.8V
VDD 1.8V, VDDQ 1.8V
Package
FBGA
FBGA
FBGA
Etron Technology, Inc.
No. 6, Technology Rd. V, Hsinchu Science Park, Hsinchu, Taiwan 30078, R.O.C.
TEL: (886)-3-5782345 FAX: (886)-3-5778671
Etron Technology, Inc. reserves the right to change products or specification without notice.




EM68C16CWQE pdf, 반도체, 판매, 대치품
EtronTech
EM68C16CWQE
Figure 3. State Diagram
OCD
calibration
Setting
MR,
EMR(1)
EMR(2)
EMR(3)
CKEL
Active
Power
Down
WR
Writing
WRA
Writing
With
Autoprecharge
Initialization
Sequence
PR
(E)MRS
Idle
All banks
precharged
ACT
SCRKFEH
CKCEKHEL
CKEL
Activating
CKEL
Self
Refreshing
REF
Refreshing
Precharge
Power
Down
CKEL
CKEL
Automatic Sequence
Cammand Sequence
CKEH
CKEL
WR
Bank
Active
WR
WRA
RD RD
Reading
RD
RDA
RDA
PR, PRA
PR, PRA
RDA
PR, PRA
Reading
With
Autoprecharge
Precharging
CKEL = CKE LOW, enter Power Down
CKEH = CKE HIGH, exit Power Down,exit Self Refresh
ACT = Activate
WR(A) = Write (with Autoprecharge)
RD(A) = Read (with Autoprecharge)
PR(A) = Precharge (All)
(E)MRS = (Extended) Mode Register Set
SRF = Enter Self Refresh
REF = Refresh
Note: Use caution with this diagram. It is indented to provide a floorplan of the possible state transitions and the
commands to control them, not all details. In particular situations involving more than one bank,
enabling/disabling on-die termination, Power Down entry/exit, timing restrictions during state transitions, among
other things, are not captured in full detail.
Rev. 1.6
4
May /2016

4페이지










EM68C16CWQE 전자부품, 판매, 대치품
EtronTech
EM68C16CWQE
Operation Mode
The following tables provide a quick reference of available DDR2 SDRAM commands, including CKE power-down
modes and bank-to-bank commands.
Table 4. Truth Table (Note (1), (2))
Command
State CKEn-1 CKEn DM BA0-2 A10 A0-9, 11-12 CS# RAS# CAS# WE#
BankActivate
Idle(3) H
HX
V Row address L
L HH
Single Bank Precharge
Any H H X V L
X
L LHL
All Banks Precharge
Any H H X X H
X
L LHL
Write
Write with AutoPrecharge
Active(3)
Active(3)
H
H
HX
HX
V L Column L H L
address
V H (A0 A9) L H L
L
L
Read
Read and Autoprecharge
Active(3)
Active(3)
H
H
HX
HX
V L Column L H L H
address
V H (A0 A9) L H L H
(Extended) Mode Register Set Idle H H X V
OP code
LLLL
No-Operation
Any H X X X X
X
L HHH
Device Deselect
Any H X X X X
X
HXXX
Refresh
Idle H H X X X
X
L L LH
SelfRefresh Entry
Idle H L X X X
X
L L LH
SelfRefresh Exit
Idle L H X X X
X
HXXX
L HHH
Power Down Mode Entry
Idle H L X X X
X
HXXX
L HHH
Power Down Mode Exit
Any L H X X X
X
HXXX
L HHH
Data Input Mask Disable
Active H
XL
XX
X
XXXX
Data Input Mask Enable(4)
Active H
XH
XX
X
XXXX
NOTE 1: V=Valid data, X=Don't Care, L=Low level, H=High level
NOTE 2: CKEn signal is input level when commands are provided.
CKEn-1 signal is input level one clock cycle before the commands are provided.
NOTE 3: These are states of bank designated by BA signal.
NOTE 4: LDM and UDM can be enabled respectively.
Rev. 1.6
7
May /2016

7페이지


구       성 총 30 페이지수
다운로드[ EM68C16CWQE.PDF 데이터시트 ]

당사 플랫폼은 키워드, 제품 이름 또는 부품 번호를 사용하여 검색할 수 있는

포괄적인 데이터시트를 제공합니다.


구매 문의
일반 IC 문의 : 샘플 및 소량 구매
-----------------------------------------------------------------------

IGBT, TR 모듈, SCR 및 다이오드 모듈을 포함한
광범위한 전력 반도체를 판매합니다.

전력 반도체 전문업체

상호 : 아이지 인터내셔날

사이트 방문 :     [ 홈페이지 ]     [ 블로그 1 ]     [ 블로그 2 ]



관련 데이터시트

부품번호상세설명 및 기능제조사
EM68C16CWQE

64M x 16 bit DDRII Synchronous DRAM

Etron Technology
Etron Technology
EM68C16CWQG

64M x 16 bit DDRII Synchronous DRAM

Etron Technology
Etron Technology

DataSheet.kr       |      2020   |     연락처      |     링크모음      |      검색     |      사이트맵