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74ACTQ573 데이터시트 PDF




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부품번호 74ACTQ573 기능
기능 Quiet Series Octal Latch
제조업체 Fairchild Semiconductor
로고 Fairchild Semiconductor 로고


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74ACTQ573 데이터시트, 핀배열, 회로
January 1990
Revised October 2000
74ACQ573 74ACTQ573
Quiet SeriesOctal Latch with 3-STATE Outputs
General Description
The ACQ/ACTQ573 is a high-speed octal latch with buff-
ered common Latch Enable (LE) and buffered common
Output Enable (OE) inputs. The ACQ/ACTQ573 is func-
tionally identical to the ACQ/ACTQ373 but with inputs and
outputs on opposite sides of the package. The ACQ/ACTQ
utilizes Fairchild’s Quiet Seriestechnology to guarantee
quiet output switching and improved dynamic threshold
performance. FACT Quiet Seriesfeatures GTOoutput
control and undershoot corrector in addition to a split
ground bus for superior performance.
Features
s ICC and IOZ reduced by 50%
s Guaranteed simultaneous switching noise level and
dynamic threshold performance
s Guaranteed pin-to-pin skew AC performance
s Improved latch-up immunity
s Inputs and outputs on opposite sides of package allow
easy interface with microprocessors
s Outputs source/sink 24 mA
Ordering Code:
Order Number Package Number
Package Description
74ACQ573SC
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74ACQ573SJ
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74ACQ573MTC
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74ACQ573PC
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
74ACTQ573SC
M20B
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300 Wide
74ACTQ573SJ
M20D
20-Lead Small Outline Package (SOP), EIAJ TYPE II, 5.3mm Wide
74ACTQ573QSC
MQA20
20-Lead Quarter Size Outline Package (QSOP), JEDEC MO-137, 0.150 Wide
74ACTQ573MTC
MTC20
20-Lead Thin Shrink Small Outline Package (TSSOP), JEDEC MO-153, 4.4mm Wide
74ACTQ573PC
N20A
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300 Wide
Device also available in Tape and Reel. Specify by appending suffix letter Xto the ordering code.
Logic Symbols
Connection Diagram
IEEE/IEC
Pin Descriptions
Pin Names
Description
D0D7
LE
Data Inputs
Latch Enable Input
OE 3-STATE Output Enable Input
O0O7
3-STATE Latch Outputs
FACT, Quiet Series, FACT Quiet Series, and GTOare trademarks of Fairchild Semiconductor Corporation
© 2000 Fairchild Semiconductor Corporation DS010633
www.fairchildsemi.com




74ACTQ573 pdf, 반도체, 판매, 대치품
DC Electrical Characteristics for ACQ (Continued)
Symbol
Parameter
VCC
TA = +25°C
TA = −40°C to +85°C
Units
(V) Typ
Guaranteed Limits
Conditions
VOLV
VIHD
Quiet Output
Minimum Dynamic VOL
Minimum HIGH Level
Dynamic Input Voltage
5.0
0.6
1.2
5.0 3.1 3.5
Figures 1, 2
V
(Note 5)(Note 6)
V (Note 5)(Note 7)
VILD Maximum LOW Level
Dynamic Input Voltage
5.0 1.9 1.5
V (Note 5)(Note 7)
Note 2: All outputs loaded; thresholds on input associated with output under test.
Note 3: Maximum test duration 2.0 ms, one output loaded at a time.
Note 4: IIN and ICC @ 3.0V are guaranteed to be less than or equal to the respective limit @ 5.5V VCC.
Note 5: Plastic DIP package.
Note 6: Max number of outputs defined as (n). Data Inputs are driven 0V to 5V. One output @ GND.
Note 7: Max number of Data Inputs (n) switching. (n 1) Inputs switching 0V to 5V (ACQ). Input-under-test switching: 5V to threshold (VILD),
0V to threshold (VIHD), f = 1 MHz.
DC Electrical Characteristics for ACTQ
Symbol
Parameter
VCC
TA = +25°C
TA = −40°C to +85°C
Units
(V) Typ
Guaranteed Limits
Conditions
VIH Minimum HIGH Level
Input Voltage
VIL Maximum LOW Level
Input Voltage
VOH Minimum HIGH Level
Output Voltage
4.5 1.5 2.0 2.0 V VOUT = 0.1V
5.5 1.5 2.0
2.0
or VCC 0.1V
4.5 1.5 0.8 0.8 V VOUT = 0.1V
5.5 1.5 0.8
0.8
or VCC 0.1V
4.5 4.49 4.4
4.4
5.5 5.49 5.4 5.4 V IOUT = −50 µA
VOL Maximum LOW Level
Output Voltage
4.5 3.86
5.5 4.86
4.5 0.001 0.1
5.5 0.001 0.1
3.76
4.76
0.1
0.1
VIN = VIL or VIH
V IOH = −24 mA
IOH = −24 mA (Note 8)
V IOUT = 50 µA
IIN Maximum Input
Leakage Current
VIN = VIL or VIH
4.5
0.36
0.44
V IOL = 24 mA
5.5
0.36
0.44
IOL = 24 mA (Note 8)
5.5
±0.1
±1.0
µA VI = VCC, GND
IOZ
ICCT
IOLD
IOHD
ICC
VOLP
VOLV
VIHD
Maximum 3-STATE
Leakage Current
Maximum ICC/Input
Minimum Dynamic
Output Current (Note 9)
Maximum Quiescent Supply Current
Quiet Output
Maximum Dynamic VOL
Quiet Output
Minimum Dynamic VOL
Minimum HIGH Level
Dynamic Input Voltage
5.5
5.5
5.5
5.5
5.5
5.0
5.0
5.0
±0.25
0.6
4.0
1.1 1.5
0.6 1.2
1.9 2.2
±2.5
1.5
75
75
40.0
µA VI = VIL, VIH
VO = VCC, GND
mA VI = VCC 2.1V
mA VOLD = 1.65V Max
mA VOHD = 3.85V Min
µA VIN = VCC or GND
Figures 1, 2
V
(Note 10)(Note 11)
Figures 1, 2
V
(Note 10)(Note 11)
V (Note 10)(Note 12)
VILD Maximum LOW Level
Dynamic Input Voltage
5.0 1.2 0.8
V (Note 10)(Note 12)
Note 8: All outputs loaded; thresholds on input associated with output under test.
Note 9: Maximum test duration 2.0 ms, one output loaded at a time.
Note 10: Plastic DIP package.
Note 11: Max number of outputs defined as (n). Data Inputs are driven 0V to 3V. One output @ GND.
Note 12: Max number of data inputs (n) switching. (n 1) inputs switching 0V to 3V (ACTQ). Input-under-test switching: 3V to threshold (VILD),
0V to threshold (VIHD), f =1 MHz.
www.fairchildsemi.com
4

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74ACTQ573 전자부품, 판매, 대치품
FACT Noise Characteristics
The setup of a noise characteristics measurement is critical
to the accuracy and repeatability of the tests. The following
is a brief description of the setup used to measure the
noise characteristics of FACT.
Equipment:
Hewlett Packard Model 8180A Word Generator
PC-163A Test Fixture
Tektronics Model 7854 Oscilloscope
Procedure:
1. Verify Test Fixture Loading: Standard Load 50 pF,
500.
2. Deskew the HFS generator so that no two channels
have greater than 150 ps skew between them. This
requires that the oscilloscope be deskewed first. It is
important to deskew the HFS generator channels
before testing. This will ensure that the outputs switch
simultaneously.
3. Terminate all inputs and outputs to ensure proper load-
ing of the outputs and that the input levels are the cor-
rect voltage.
4. Set the HFS generator to toggle all but one output at a
frequency of 1 MHz. Greater frequencies will increase
DUT heating and affect the results of the measure-
ment.
5. Set the HFS generator input levels at 0V LOW and 3V
HIGH for ACT devices and 0V LOW and 5V HIGH for
AC devices. Verify levels with an oscilloscope.
VOLP/VOLV and VOHP/VOHV:
Determine the quiet output pin that demonstrates the
greatest noise levels. The worst case pin will usually be
the furthest from the ground pin. Monitor the output volt-
ages using a 50coaxial cable plugged into a standard
SMB type connector on the test fixture. Do not use an
active FET probe.
Measure VOLP and VOLV on the quiet output during the
worst case transition for active and enable. Measure
VOHP and VOHV on the quiet output during the worst
case active and enable transition.
Verify that the GND reference recorded on the oscillo-
scope has not drifted to ensure the accuracy and repeat-
ability of the measurements.
VILD and VIHD:
Monitor one of the switching outputs using a 50coaxial
cable plugged into a standard SMB type connector on
the test fixture. Do not use an active FET probe.
First increase the input LOW voltage level, VIL, until the
output begins to oscillate or steps out a min of 2 ns.
Oscillation is defined as noise on the output LOW level
that exceeds VIL limits, or on output HIGH levels that
exceed VIH limits. The input LOW voltage level at which
oscillation occurs is defined as VILD.
Next decrease the input HIGH voltage level, VIH, until
the output begins to oscillate or steps out a min of 2 ns.
Oscillation is defined as noise on the output LOW level
that exceeds VIL limits, or on output HIGH levels that
exceed VIH limits. The input HIGH voltage level at which
oscillation occurs is defined as VIHD.
Verify that the GND reference recorded on the oscillo-
scope has not drifted to ensure the accuracy and repeat-
ability of the measurements.
Note 19: VOHV and VOLP are measured with respect to ground reference.
Note 20: Input pulses have the following characteristics:
f = 1 MHz, tr = 3 ns, tf = 3 ns, skew < 150 ps.
FIGURE 1. Quiet Output Noise Voltage Waveforms
FIGURE 2. Simultaneous Switching Test Circuit
7 www.fairchildsemi.com

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