|
|
PDF KSZ8091RNB Data sheet ( Hoja de datos )
| Número de pieza | KSZ8091RNB | |
| Descripción | 10Base-T/100Base-TX Physical Layer Transceiver | |
| Fabricantes | Micrel Semiconductor | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de KSZ8091RNB (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
|
No Preview Available !
KSZ8091MNX/KSZ8091RNB
10Base-T/100Base-TX
Physical Layer Transceiver
Revision 1.2
General Description
The KSZ8091 is a single-supply 10Base-T/100Base-TX
Ethernet physical-layer transceiver for transmission and
reception of data over standard CAT-5 unshielded twisted
pair (UTP) cable.
The KSZ8091 is a highly-integrated PHY solution. It reduces
board cost and simplifies board layout by using on-chip
termination resistors for the differential pairs, by integrating a
low-noise regulator to supply the 1.2V core, and by offering a
flexible 1.8/2.5/3.3V digital I/O interface.
The KSZ8091MNX offers the Media Independent Interface
(MII) and the KSZ8091RNB offers the Reduced Media
Independent Interface (RMII) for direct connection with
MII/RMII-compliant Ethernet MAC processors and
switches.
Energy Efficient Ethernet (EEE) provides further power
saving during idle traffic periods and Wake-on-LAN (WOL)
provides a mechanism for the KSZ8091 to wake up a
system that is in standby power mode.
The KSZ8091 provides diagnostic features to facilitate
system bring-up and debugging in production testing and
in product deployment. Parametric NAND tree support
enables fault detection between KSZ8091 I/Os and the
board. Micrel LinkMD® TDR-based cable diagnostics
identify faulty copper cabling.
The KSZ8091MNX and KSZ8091RNB are available in 32-
pin, lead-free QFN packages (see “Ordering Information”).
Datasheets and support documentation are available on
website at: www.micrel.com.
Features
• Single-chip 10Base-T/100Base-TX IEEE 802.3
compliant Ethernet transceiver
• MII interface support (KSZ8091MNX)
• RMII v1.2 interface support with a 50MHz reference
clock output to MAC, and an option to input a 50MHz
reference clock (KSZ8091RNB)
• Back-to-back mode support for a 100Mbps copper
repeater
• MDC/MDIO management interface for PHY register
configuration
• Programmable interrupt output
• LED outputs for link and activity status indication, plus
speed indication for KSZ8091RNB
• On-chip termination resistors for the differential pairs
• Baseline wander correction
• HP Auto MDI/MDI-X to reliably detect and correct
straight-through and crossover cable connections with
disable and enable option
• Auto-negotiation to automatically select the highest link-
up speed (10/100Mbps) and duplex (half/full)
• Energy Efficient Ethernet (EEE) support with low-power
idle (LPI) mode and clock stoppage (MII version only)
for 100Base-TX and transmit amplitude reduction with
10Base-Te option
• Wake-on-LAN (WOL) support with either magic packet,
link status change, or robust custom-packet detection
• HBM ESD rating (6kV)
Functional Diagram
LinkMD is a registered trademark of Micrel, Inc.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
August 31, 2015
Revision 1.2
1 page  
Micrel, Inc.
KSZ8091MNX/KSZ8091RNB
Energy Efficient Ethernet (EEE)............................................................................................................................................ 38
Transmit Direction Control (MAC-to-PHY) ........................................................................................................................ 39
Receive Direction Control (PHY-to-MAC) ......................................................................................................................... 40
Registers Associated with EEE ......................................................................................................................................... 41
Wake-On-LAN ....................................................................................................................................................................... 42
Magic-Packet Detection..................................................................................................................................................... 42
Customized-Packet Detection ........................................................................................................................................... 43
Link Status Change Detection ........................................................................................................................................... 43
Reference Circuit for Power and Ground Connections......................................................................................................... 44
Typical Current/Power Consumption .................................................................................................................................... 45
Transceiver (3.3V), Digital I/Os (3.3V) .............................................................................................................................. 45
Transceiver (3.3V), Digital I/Os (2.5V) .............................................................................................................................. 45
Transceiver (3.3V), Digital I/Os (1.8V) .............................................................................................................................. 46
Register Map ......................................................................................................................................................................... 47
Standard Registers ............................................................................................................................................................... 49
IEEE-Defined Registers – Descriptions............................................................................................................................. 49
Vendor-Specific Registers – Descriptions ......................................................................................................................... 54
MMD Registers...................................................................................................................................................................... 60
MMD Registers – Descriptions .......................................................................................................................................... 61
Absolute Maximum Ratings .................................................................................................................................................. 66
Operating Ratings ................................................................................................................................................................. 66
Electrical Characteristics....................................................................................................................................................... 66
Timing Diagrams ................................................................................................................................................................... 68
MII SQE Timing (10Base-T) .............................................................................................................................................. 68
MII Transmit Timing (10Base-T)........................................................................................................................................ 69
MII Receive Timing (10Base-T)......................................................................................................................................... 70
MII Transmit Timing (100Base-TX) ................................................................................................................................... 71
MII Receive Timing (100Base-TX) .................................................................................................................................... 72
RMII Timing ....................................................................................................................................................................... 73
Auto-Negotiation Timing .................................................................................................................................................... 74
MDC/MDIO Timing ............................................................................................................................................................ 75
Power-Up/Reset Timing .................................................................................................................................................... 76
Reset Circuit.......................................................................................................................................................................... 77
Reference Circuits – LED Strap-In Pins................................................................................................................................ 78
Reference Clock – Connection and Selection ...................................................................................................................... 79
Magnetic – Connection and Selection .................................................................................................................................. 80
Package Information ............................................................................................................................................................. 82
August 31, 2015
5
Revision 1.2
5 Page 
Micrel, Inc.
KSZ8091MNX/KSZ8091RNB
Pin Description – KSZ8091MNX (Continued)
Pin Number
24
25
26
27
Pin Name
TXD0
TXD1
TXD2
TXD3
Type(2)
I
I
I
I
Pin Function
MII mode: MII Transmit Data Input[0](4)
MII mode: MII Transmit Data Input[1](4)
MII mode: MII Transmit Data Input[2](4)
MII Mode: MII Transmit Data Input[3](4)
28
COL/
Ipd/O MII mode: MII Collision Detect output
CONFIG0
Config mode: The pull-up/pull-down value is latched as CONFIG0 at the de-assertion
of reset.
See the “Strapping Options – KSZ8091MNX” section for details.
29
CRS/
Ipd/O MII mode: MII Carrier Sense output
CONFIG1
Config mode: The pull-up/pull-down value is latched as CONFIG1 at the de-assertion
of reset.
See the “Strapping Options – KSZ8091MNX” section for details.
30
LED0/
Ipu/O LED output:
Programmable LED0 output
PME_N1/
PME_N Output: Programmable PME_N Output (pin option 1)
In this mode, this pin has a weak pull-up, is an open-drain, and
requires an external 1.0kΩ pull-up resistor to VDDIO (digital VDD).
NWAYEN
Config mode: Latched as auto-negotiation enable (Register 0h, bit [12]) at the de-
assertion of reset.
See the “Strapping Options – KSZ8091MNX” section for details.
The LED0 pin is programmable using Register 1Fh bits [5:4], and is defined as follows.
LED mode = [00]
Link/Activity
Pin State
No link
High
Link Low
Activity
Toggle
LED mode = [01]
Link
Pin State
No link
High
Link Low
LED Definition
OFF
ON
Blinking
LED Definition
OFF
ON
31
32
PADDLE
TXER
RST#
GND
Ipd
Ipu
GND
LED mode = [10], [11] Reserved
MII mode: MII Transmit Error input
For EEE mode, this pin is driven by the EEE-MAC to put the KSZ8091MNX transmit
into the LPI state.
For non-EEE mode, this pin is not defined for error transmission from MAC to
KSZ8091MNX and can be left as a no connect.
Chip reset (active low)
Ground
August 31, 2015
11
Revision 1.2
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet KSZ8091RNB.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| KSZ8091RNB | 10BASE-T/100BASE-TX Physical Layer Transceiver |  Microchip |
| KSZ8091RNB | 10Base-T/100Base-TX Physical Layer Transceiver | Micrel Semiconductor |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |