PDF KSZ8441FHL Data sheet ( Hoja de datos )

Número de pieza	KSZ8441FHL
Descripción	IEEE 1588v2-enabled Ethernet controller device
Fabricantes	Micrel Semiconductor
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No Preview Available ! KSZ8441HL/FHL IEEE 1588v2, Precision Time Protocol-Enabled, 10/100Mbs, Ethernet End-Point Connection with 8- or 16-Bit Host Bus Interface Revision 1.0 General Description The KSZ8441 product is an IEEE 1588v2-enabled Ethernet controller device with an internal MAC and PHY that provides integrated communication and synchronization for a range of industrial Ethernet applications. The KSZ8441 product enables end-point connection in a centralized topology. A flexible 8- or 16-bit general bus interface is provided for interfacing to an external host processor. The KSZ8441 devices incorporate the IEEE 1588v2 protocol. Sub-microsecond synchronization is available via the use of hardware-based time stamping and transparent clocks making it the ideal solution for time-synchronized layer 2 communication in critical industrial applications. Extensive general purpose input/output (GPIO) capabilities are available to use with the IEEE 1588v2 PTP to efficiently and accurately interface to locally-connected devices. Complementing the industry’s most integrated IEEE 1588v2 device is a precision timing protocol (PTP) v2 software stack that has been pre-qualified with the KSZ84xx product family. The PTP stack has been optimized around the KSZ84xx chip architecture, and is available in source code format along with Micrel’s chip driver. ETHERSYNCH™ The KSZ8441 is built upon Micrel’s industry-leading Ethernet technology, with features designed-to-offload host processing and streamline overall design, including: • 1 integrated 10/100BASE-TX PHY transceiver, featuring the industry’s lowest power consumption • Flexible management options that support common standard interfaces A robust assortment of power management features including energy-efficient Ethernet (EEE) have been designed in to satisfy energy-efficient environments. Datasheets and support documentation are available on Micrel’s web site at: www.micrel.com. ETHERSYNCH is a trademark of Micrel, Inc. Magic Packet is a trademark of Advanced Micro Devices. LinkMD is a registered trademark of Micrel, Inc. Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com June 17, 2014 Revision -1.0 1 page Micrel, Inc. KSZ8441HL/FHL Contents Acronyms .............................................................................................................................................................................. 15 Pin Configuration................................................................................................................................................................... 17 Pin Description ...................................................................................................................................................................... 18 Strapping Options ................................................................................................................................................................. 24 Functional Description........................................................................................................................................................... 25 Phy (Physical) Block ............................................................................................................................................................. 26 100BASE-TX Transmit ...................................................................................................................................................... 26 100BASE-TX Receive ....................................................................................................................................................... 26 Scrambler/De-scrambler (100BASE-TX only) ................................................................................................................... 26 PLL Clock Synthesizer (Recovery).................................................................................................................................... 26 100BASE-FX Operation .................................................................................................................................................... 26 100BASE-FX Signal Detection .......................................................................................................................................... 27 100BASE-FX Far-End Fault.................................................................................................................................................. 27 10BASE-T Transmit........................................................................................................................................................... 27 10BASE-T Receive............................................................................................................................................................ 27 MDI/MDI-X Auto Crossover ............................................................................................................................................... 27 Straight Cable ................................................................................................................................................................ 28 Crossover Cable ............................................................................................................................................................ 28 Auto-Negotiation ................................................................................................................................................................... 29 LinkMD® Cable Diagnostics .................................................................................................................................................. 30 Access............................................................................................................................................................................ 30 Usage............................................................................................................................................................................. 30 On-chip Termination Resistors.......................................................................................................................................... 30 Loopback Support ................................................................................................................................................................. 31 Near-End (Remote) Loopback ....................................................................................................................................... 31 Far-End (Local) Loopback ............................................................................................................................................. 31 MAC (Media Access Controller) Block.................................................................................................................................. 32 MAC Operation.................................................................................................................................................................. 32 Inter-Packet Gap (IPG)...................................................................................................................................................... 32 Back-Off Algorithm ............................................................................................................................................................ 32 Late Collision ..................................................................................................................................................................... 32 Legal Packet Size.............................................................................................................................................................. 32 Flow Control ...................................................................................................................................................................... 32 Half-Duplex Backpressure................................................................................................................................................. 32 Address Filtering Function .................................................................................................................................................... 33 Queue Management Unit (QMU) .......................................................................................................................................... 34 Transmit Queue (TXQ) Frame Format .............................................................................................................................. 34 Frame Transmitting Path Operation in TXQ...................................................................................................................... 35 Driver Routine for Transmitting Packets from Host Processor to KSZ8441 ..................................................................... 36 Receive Queue (RXQ) Frame Format............................................................................................................................... 37 Frame Receiving Path Operation in RXQ ......................................................................................................................... 37 Driver Routine for Receiving Packets from the KSZ8441 to the Host Processor ............................................................. 38 IEEE 1588 Precision Time Protocol (PTP) Block.................................................................................................................. 40 IEEE 1588 PTP Clock Types ................................................................................................................................................ 41 IEEE 1588 PTP One-Step or Two-Step Clock Operation..................................................................................................... 41 One-Step Clock Operation: ............................................................................................................................................... 41 Two-Step Clock Operation: ............................................................................................................................................... 41 IEEE 1588 PTP Best Master Clock Selection....................................................................................................................... 41 IEEE 1588 PTP System Time Clock..................................................................................................................................... 42 Updating the System time Clock.................................................................................................................................... 43 Directly Setting or Reading the Time................................................................................................................................. 43 Step Time Adjustment ....................................................................................................................................................... 43 Continuous Time Adjustment ............................................................................................................................................ 43 Temporary Time Adjustment ............................................................................................................................................. 43 PTP Clock Initialization...................................................................................................................................................... 43 IEEE 1588 PTP Message Processing .................................................................................................................................. 45 June 17, 2014 5 Revision 1.0 5 Page Micrel, Inc. KSZ8441HL/FHL Timestamp Unit 12 Status/Configuration/Control and Input 1st Sample Time Registers (0x580 – 0x58D) ....................... 160 0x58E – 0x593: Reserved................................................................................................................................................... 160 Timestamp Unit 12 Input 2nd Sample Time Registers (0x594 – 0x59D) ........................................................................... 160 0x59E – 0x5A3: Reserved .................................................................................................................................................. 160 Timestamp Unit 12 Input 3rd Sample Time Registers (0x5A4 – 0x5AD) ........................................................................... 160 0x5AE – 0x5B3: Reserved .................................................................................................................................................. 160 Timestamp Unit 12 Input 4th Sample Time Registers (0x5B4 – 0x5BD)............................................................................ 160 0x5BE – 0x5C3: Reserved.................................................................................................................................................. 160 Timestamp Unit 12 Input 5th Sample Time Registers (0x5C4 – 0x5CD) ........................................................................... 161 0x5CE – 0x5D3: Reserved.................................................................................................................................................. 161 Timestamp Unit 12 Input 6th Sample Time Registers (0x5D4 – 0x5DD) ........................................................................... 161 0x5DE – 0x5E3: Reserved.................................................................................................................................................. 161 Timestamp Unit 12 Input 7th Sample Time Registers (0x5E4 – 0x5ED)............................................................................ 161 0x5EE – 0x5F3: Reserved .................................................................................................................................................. 161 Timestamp Unit 12 Input 8th Sample Time Registers (0x5F4 – 0x5FD) ............................................................................ 161 0x5FE – 0x5FF: Reserved .................................................................................................................................................. 161 Internal I/O Registers Space Mapping for PTP 1588 Clock and Global Control (0x600 – 0x7FF)..................................... 161 PTP Clock Control Register (0x600 – 0x601): PTP_CLK_CTL .......................................................................................... 161 0x602 – 0x603: Reserved ................................................................................................................................................... 162 PTP Real Time Clock in Nanoseconds Low-Word Register (0x604 – 0x605): PTP_RTC_NSL ........................................ 162 PTP Real Time Clock in Nanoseconds High-Word Register (0x606 – 0x607): PTP_RTC_NSH....................................... 162 PTP Real Time Clock in Seconds Low-Word Register (0x608 – 0x609): PTP_RTC_SL................................................... 162 PTP Real Time Clock in Seconds High-Word Register (0x60A – 0x60B): PTP_RTC_SH................................................. 163 PTP Real Time Clock in Phase Register (0x60C – 0x60D): PTP_RTC_PHASE ............................................................... 163 0x60E – 0x60F: Reserved................................................................................................................................................... 163 PTP Rate in Sub-Nanoseconds Low-Word Register (0x610 – 0x611): PTP_SNS_RATE_L............................................. 163 PTP Rate in Sub-Nanoseconds High-Word and Control Register (0x612 – 0x613): PTP_SNS_RATE_H........................ 164 PTP Temporary Adjustment Mode Duration in Low-word Register (0x614 – 0x615): PTP_TEMP_ADJ_DURA_L .......... 164 PTP Temporary Adjustment Mode Duration in High-word Register (0x616 – 0x617): PTP_TEMP_ADJ_DURA_H ......... 164 0x618 – 0x61F: Reserved ................................................................................................................................................... 164 PTP Message Configuration 1 Register (0x620 – 0x621): PTP_MSG_CFG_1 ................................................................. 165 PTP Message Configuration 2 Register (0x622 – 0x623): PTP_MSG_CFG_2 ................................................................. 166 PTP Domain and Version Register (0x624 – 0x625): PTP_DOMAIN_VER....................................................................... 167 0x626 – 0x63F: Reserved ................................................................................................................................................... 167 PTP Port 1 Receive Latency Register (0x640 – 0x641): PTP_P1_RX_LATENCY ............................................................ 167 PTP Domain and Version Register (0x624 – 0x625): PTP_DOMAIN_VER....................................................................... 168 PTP Port 1 Transmit Latency Register (0x642 – 0x643): PTP_P1_TX_LATENCY ........................................................... 168 PTP Port 1 Asymmetry Correction Register (0x644 – 0x645): PTP_P1_ASYM_COR ...................................................... 168 PTP Port 1 Link Delay Register (0x646 – 0x647): PTP_P1_LINK_DLY ............................................................................ 168 PTP Port 1 Egress Timestamp Low-Word Register for Pdelay_Req and Delay_Req (0x648 – 0x649): P1_XDLY_REQ_TSL .......................................................................................................................................................... 169 PTP Port 1 Egress Timestamp High-Word Register for Pdelay_Req and Delay_Req (0x64A – 0x64B): P1_XDLY_REQ_TSH ......................................................................................................................................................... 169 PTP Port 1 Egress Timestamp Low-Word Register for Sync (0x64C – 0x64D): P1_SYNC_TSL...................................... 169 PTP Port 1 Egress Timestamp High-Word Register for Sync (0x64E – 0x64F): P1_SYNC_TSH..................................... 169 PTP Port 1 Egress Timestamp Low-Word Register for Pdelay_Resp (0x650 – 0x651): P1_PDLY_RESP_TSL .............. 170 PTP Port 1 Egress Timestamp High-Word Register for Pdelay_Resp (0x652 – 0x653): P1_PDLY_RESP_TSH............. 170 0x654 – 0x67F: Reserved ................................................................................................................................................... 170 GPIO Monitor Register (0x680 – 0x681): GPIO_MONITOR .............................................................................................. 170 GPIO Output Enable Register (0x682 – 0x683): GPIO_OEN............................................................................................. 170 0x684 – 0x687: Reserved ................................................................................................................................................... 170 PTP Trigger Unit Interrupt Status Register (0x688 – 0x689): PTP_TRIG_IS..................................................................... 171 PTP Trigger Unit Interrupt Enable Register (0x68A – 0x68B): PTP_TRIG_IE ................................................................... 171 PTP Timestamp Unit Interrupt Status Register (0x68C – 0x68D): PTP_TS_IS ................................................................. 171 PTP Timestamp Unit Interrupt Enable Register (0x68E – 0x68F): PTP_TS_IE................................................................. 172 0x690 – 0x733: Reserved ................................................................................................................................................... 172 DSP Control 1 Register (0x734 – 0x735): DSP_CNTRL_6 ................................................................................................ 172 June 17, 2014 11 Revision 1.0 11 Page

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