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부품번호 | KSZ8463FML 기능 |
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기능 | ETHERSYNCH product line consists of IEEE 1588v2 enabled Ethernet switches | ||
제조업체 | Micrel Semiconductor | ||
로고 | |||
전체 30 페이지수
KSZ8463ML/RL/FML/FRL
IEEE 1588 Precision Time Protocol-
Enabled, Three-Port, 10/100-Managed
Switch with MII or RMII
Revision 1.0
General Description
The KSZ8463 ETHERSYNCH™ product line consists of
IEEE 1588v2 enabled Ethernet switches, providing
integrated communications and synchronization for a
range of Industrial Ethernet applications.
The KSZ8463 ETHERSYNCH product line enables
distributed, daisy-chained topologies preferred for
Industrial Ethernet networks. Conventional centralized
(i.e., star-wired) topologies are also supported for dual-
homed, fault-tolerant arrangements.
A flexible set of standard MAC interfaces is provided to
interface to external host processors with embedded
Ethernet MACs:
• KSZ8463ML: Media Independent Interface (MII)
• KSZ8463RL: Reduced Media Independent Interface
(RMII)
• KSZ8463FML: MII, supports 100BASE-FX fiber in
addition to 10/100BASE-TX copper
• KSZ8463FRL: RMII, supports 100BASE-FX fiber in
addition to 10/100BASE-TX copper
The KSZ8463 devices incorporate the IEEE 1588v2
protocol. Sub-microsecond synchronization is available via
the use of hardware-based time-stamping and transparent
clocks making it the ideal solution for time synchronized
Layer 2 communication in critical industrial applications.
Extensive general purpose I/O (GPIO) capabilities are
available to use with the IEEE 1588v2 PTP to efficiently
and accurately interface to locally connected devices.
Complementing the industry’s most-integrated IEEE
1588v2 device is a precision timing protocol (PTP) v2
software stack that has been pre-qualified with the
KSZ84xx product family. The PTP stack has been
optimized around the KSZ84xx chip architecture, and is
available in source code format along with Micrel’s chip
driver.
ETHERSYNCH™
The KSZ8463 product line is built upon Micrel’s industry-
leading Ethernet technology, with features designed to
offload host processing and streamline your overall design.
• Wire-speed Ethernet switching fabric with extensive
filtering
• Two integrated 10/100BASE-TX PHY transceivers,
featuring the industry’s lowest power consumption
• Full-featured quality-of-service (QoS) support
• Flexible management options that support common
standard interfaces
The wire-speed, store-and-forward switching fabric
provides a full complement of QoS and congestion control
features optimized for real-time Ethernet.
A robust assortment of power-management features
including energy-efficient Ethernet (EEE) have been
designed in to satisfy energy efficient environments.
Datasheets and support documentation are available on
Micrel’s web site at: www.micrel.com.
Functional Diagram
ETHERSYNCH is a trademark of Micrel, Inc.
LinkMD is a registered trademark of Micrel, Inc.
Micrel Inc. • 2180 Fortune Drive • San Jose, CA 95131 • USA • tel +1 (408) 944-0800 • fax + 1 (408) 474-1000 • http://www.micrel.com
June 11, 2014
Revision 1.0
Micrel, Inc.
KSZ8463ML/RL/FML/FRL
Comprehensive Configuration Registers Access
• High-speed SPI (4-wire, up to 50 MHz) Interface to
access all internal registers
• MII Management (MIIM, MDC/MDIO 2-wire) Interface to
access all PHY registers per clause 22.2.4.5 of the IEEE
802.3 specification
• I/O pin strapping facility to set certain register bits from
I/O pins at reset time
• Control registers configurable on-the-fly
IEEE 1588v2 PTP and Clock Synchronization
• Fully compliant with the IEEE 1588v2 precision time
protocol
• One-step or two-step transparent clock (TC) timing
corrections
• E2E (end-to-end) or P2P (peer-to-peer) transparent
clock (TC)
• Grandmaster, master, slave, ordinary clock (OC)
support
• IEEE1588v2 PTP Multicast and Unicast frame support
• Transports of PTP over IPv4/IPv6 UDP and IEEE 802.3
Ethernet
• Delay request-response and peer delay mechanism
• Ingress/egress packet timestamp capture/recording and
checksum update
• Correction field update with residence time and link
delay
• IEEE1588v2 PTP packet filtering unit to reduce host
processor overhead
• A 64-bit adjustable system precision clock
• Twelve trigger output units and twelve timestamp input
units available for flexible IEEE1588v2 control of twelve
programmable GPIO[11:0] pins synchronized to the
precision time clock
• GPIO pin usage for 1 PPS generation, frequency
generator, control bit streams, event monitoring,
precision pulse generation, complex waveform
generation
Power and Power Management
• Single 3.3V power supply with optional VDD I/O for
1.8V, 2.5V or 3.3V
• Integrated low voltage (~1.3V) low-noise regulator
(LDO) output for digital and analog core power
• Supports IEEE P802.3az™ energy-efficient Ethernet
(EEE) to reduce power consumption in transceivers in
LPI state
• Full-chip hardware or software power-down (all registers
value are not saved and strap-in value will re-strap after
release the power-down)
• Energy detect power-down (EDPD), which disables the
PHY transceiver when cables are removed
• Dynamic clock tree control to reduce clocking in areas
not in use
• Power consumption less than 0.5W
Additional Features
• Single 25MHz ±50ppm reference clock requirement for
MII mode
• Selectable 25MHz or 50MHz inputs for RMII mode
• Comprehensive programmable two LED indicators
support for link, activity, full/half duplex and 10/100
speed.
• LED pins directly controllable.
• Industrial temperature range: –40°C to +85°C
• 64-pin (10mm x 10mm) lead free (ROHS) LQFP
package
• 0.11μm technology for lower power consumption
Applications
• Industrial Ethernet applications that employ IEEE 802.3-
compliant MACs. (Ethernet/IP, Profinet, MODBUS TCP,
etc)
• Real-time Ethernet networks requiring sub-microsecond
synchronization over standard Ethernet
• IEC 61850 networks supporting power substation
automation
• Networked measurement and control systems
• Industrial automation and motion control systems
• Test and measurement equipment
June 11, 2014
4
Revision 1.0
4페이지 Micrel, Inc.
KSZ8463ML/RL/FML/FRL
“Receive Only” Mirror-on-a-Port .................................................................................................................................... 43
“Transmit Only” Mirror-on-a-Port ................................................................................................................................... 43
“Receive and Transmit” Mirror-on-Two-Ports ................................................................................................................ 43
IEEE 802.1Q VLAN Support .......................................................................................................................................... 43
Quality-of-Service (QoS) Priority Support ......................................................................................................................... 44
Port-Based Priority ............................................................................................................................................................ 44
802.1p-Based Priority ........................................................................................................................................................ 44
802.1p Priority Field Re-Mapping ...................................................................................................................................... 45
DiffServ-Based Priority ...................................................................................................................................................... 45
Rate Limiting Support ........................................................................................................................................................ 45
MAC Address Filtering Function........................................................................................................................................ 46
IEEE 1588 Precision Time Protocol (PTP) Block.................................................................................................................. 47
IEEE 1588 PTP Clock Types............................................................................................................................................. 48
IEEE 1588 PTP One-Step or Two-Step Clock Operation ................................................................................................. 48
IEEE 1588 PTP Best Master Clock Selection ................................................................................................................... 48
IEEE 1588 PTP System Time Clock ................................................................................................................................. 48
Updating the System Time Clock ...................................................................................................................................... 50
Directly Setting or Reading the Time ............................................................................................................................. 50
Step-Time Adjustment ................................................................................................................................................... 50
Continuous Time Adjustment......................................................................................................................................... 50
Temporary Time Adjustment ......................................................................................................................................... 50
PTP Clock Initialization .................................................................................................................................................. 51
IEEE 1588 PTP Message Processing ............................................................................................................................... 51
IEEE 1588 PTP Ingress Packet Processing .................................................................................................................. 51
IEEE 1588 PTP Egress Packet Processing................................................................................................................... 51
IEEE 1588 PTP Event Triggering and Timestamping ....................................................................................................... 52
IEEE 1588 PTP Trigger Output ..................................................................................................................................... 52
IEEE 1588 PTP Event Timestamp Input........................................................................................................................ 52
IEEE 1588 PTP Event Interrupts ................................................................................................................................... 53
IEEE 1588 GPIO ............................................................................................................................................................ 53
General Purpose and IEEE 1588 Input/Output (GPIO) ........................................................................................................ 54
Overview............................................................................................................................................................................ 54
GPIO Pin Functionality Control.......................................................................................................................................... 54
GPIO Pin Control Register Layout..................................................................................................................................... 55
GPIO Trigger Output Unit and Timestamp Unit Interrupts ................................................................................................ 57
Using the GPIO Pins with the Trigger Output Units .............................................................................................................. 59
Creating a Low-Going Pulse at a Specific Time................................................................................................................ 59
Creating a High-Going Pulse at a Specific Time ............................................................................................................... 59
Creating a Free Running Clock Source............................................................................................................................. 60
Creating Finite Length Periodic Bit Streams at a Specific Time........................................................................................ 61
Creating Finite Length Non-Uniform Bit Streams at a Specific Time ................................................................................ 61
Creating Complex Waveforms at a Specific Time............................................................................................................. 62
Using the GPIO Pins with the Timestamp Input Units .......................................................................................................... 64
Device Clocks........................................................................................................................................................................ 66
GPIO and IEEE 1588-Related Clocking............................................................................................................................ 67
Power .................................................................................................................................................................................... 68
Internal Low Voltage LDO Regulator................................................................................................................................. 69
Power Management .............................................................................................................................................................. 70
Normal Operation Mode .................................................................................................................................................... 70
Energy-Detect Mode.......................................................................................................................................................... 70
Global Soft Power-Down Mode ......................................................................................................................................... 71
Energy-Efficient Ethernet (EEE) ........................................................................................................................................ 71
Transmit Direction Control for MII Mode ........................................................................................................................... 72
Receive Direction Control for MII Mode ............................................................................................................................ 72
Registers Associated with EEE ......................................................................................................................................... 72
Interrupt Generation on Power Management-Related Events.............................................................................................. 72
Interfaces............................................................................................................................................................................... 73
June 11, 2014
7
Revision 1.0
7페이지 | |||
구 성 | 총 30 페이지수 | ||
다운로드 | [ KSZ8463FML.PDF 데이터시트 ] |
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부품번호 | 상세설명 및 기능 | 제조사 |
KSZ8463FML | ETHERSYNCH product line consists of IEEE 1588v2 enabled Ethernet switches | Micrel Semiconductor |
DataSheet.kr | 2020 | 연락처 | 링크모음 | 검색 | 사이트맵 |