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PDF AOZ5066 Data sheet ( Hoja de datos )
| Número de pieza | AOZ5066 | |
| Descripción | 60A DrMOS Power Module | |
| Fabricantes | Alpha & Omega Semiconductors | |
| Logotipo |  |
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AOZ5066
60A DrMOS Power Module
General Description
The AOZ5066 is a high efficiency synchronous buck
power stage module consisting of two asymmetrical
MOSFETs and an integrated driver. The MOSFETs are
individually optimized for operation in the synchronous
buck configuration. The high side MOSFET has low
capacitance and gate charge for fast switching with low
duty cycle operation. The low side MOSFET has ultra low
RDS(ON) to minimize conduction losses.
The AOZ5066 is available with two PWM options.
AOZ5066QI is intended for use with TTL compatible
PWM inputs. AOZ5066QI-01 has lower thresholds on the
PWM signal and can operate with 3V inputs. All other
parameters are identical for the two versions. Both
versions are tri-state compatible that allows both power
MOSFETs to be turned off.
A number of features are provided making the AOZ5066
a highly versatile power module. The boot supply diode is
integrated in the driver. The low side MOSFET can be
driven into diode emulation mode to provide
asynchronous operation when required. The pinout is
optimized for low inductance routing of the converter
keeping the parasitics and their effects to the minimum.
Features
Fully complies with Intel DrMOS Rev 4.0 specifications
4.5V to 25V input voltage range
4.5V to 5.5V driver supply range
Up to 60A output current
Up to 1MHz PWM operation
Tri state PWM input
Undervoltage protection
Integrated boot supply diode
Diode Emulation mode of operation
Thermal shutdown alarm with flag
Small 6x6 QFN-40L package
Applications
Servers
VRMs for motherboards
Point of load DC/DC converters
Memory and graphic cards
Video gaming consoles
Typical Application Circuit
+5V
PWM
Controller
CGND
VDRV
VCIN
PWM
SMOD
DISB#
THDN
AOZ5066
Drive Logic
and
Dead Time
Control
VIN
BOOT
Cboot
VSWH
CGND
PGND
VIN
12V
Lout VOUT
Cin Cout
PGND
Rev. 3.0 December 2013
www.aosmd.com
Page 1 of 16
1 page  
Electrical Characteristics(3) (Continued)
TA = 25°C, VIN = 12V, VDRV = VCIN = 5V unless otherwise specified.
Symbol
Parameter
Conditions
PWM INPUT (AOZ5066QI-01)
VPWMH
VPWML
IPWM
VTRIH
PWM Input High Threshold
PWM Input Low Threshold
PWM Pin Input Current
PWM Input Tri State
Threshold
VTRIL
VTRRH
VTRFH
Tri State Threshold
Hysteresis
DISB# INPUT
VDISBON Outputs Enable Threshold
VDISBOFF Outputs Disable Threshold
IDISB
DISB# pin input current
SMOD INPUT
VSMODH SMOD Enable Threshold
VSMODL SMOD Disable Threshold
ISMOD SMOD Pin Input Current
GATE DRIVER TIMINGS
tPDLU
PWM to HS Gate
tPDLL
PWM to LS Gate
tPDHU LS to HS Gate Deadtime
tPDHL
HS to LS Gate Deadtime
tTSSHD Tri State Shutdown Delay
tPTS Tri State Propagation Delay
THERMAL SHUTDOWN(5)
TJTHDN
TJHYST
VTHDNL
RTHDNL
Shutdown Threshold
Hysteresis
THDN Pin Output Low
THDN Pull Down
Resistance
VPWM Rising, VCIN = 5V
VPWM Falling, VCIN = 5V
Source or Sink, VPWM = 0V to 3V
VPWM Rising, VCIN = 5V
VPWM Falling, VCIN = 5V
VPWM Rising, VCIN = 5V
VPWM Falling, VCIN = 5V
VCIN = 5V
VCIN = 5V
Source or Sink
VCIN = 5V
VCIN = 5V
Source or Sink
PWM H L, GH H L
PWM L H, GL H L
GL H L, GH L H
GH H L, GL L H
5k pull up resistor to VCIN
Notes:
3. All voltages are specified with respect to the corresponding GND pin
4. Characterisation value. Not tested in production.
5. Temperature sensed on the driver pad
AOZ5066
Min. Typ. Max. Units
1.8 2.0 2.2 V
0.8 1.0 1.2 V
±10 A
1.0 1.3 1.6 V
1.5 1.75 2.0
V
300 mV
300 mV
2.0 V
0.8 V
±10 A
2.0 V
0.8 V
±10 A
20 ns
35 ns
16 ns
17 ns
170 ns
35 ns
150 °C
15 °C
0.06 V
60
Rev. 3.0 December 2013
www.aosmd.com
Page 5 of 16
5 Page 
AOZ5066
Table 1. PWM Input and Tri State Thresholds
Thresholds
AOZ5066QI
AOZ5066QI-01
VPWMH
3.9V
2V
VPWML
1.0V
1V
VTRIH
1.3V
1.3V
VTRIL
3.7V
1.75V
Note: See Figure 13 for propagation delays and tri state window.
Diode Mode Emulation of Low Side MOSFET (SMOD)
AOZ5066QI can be operated in the diode emulation or
skip mode using the SMOD pin. This is useful if the
converter has to operate in asynchronous mode during
start up, light load or under pre bias conditions. If SMOD
is taken high, the controller will use the PWM signal as
reference and generate both the high and low side
complementary gate drive outputs with the minimal
delays necessary to avoid cross conduction. When the
pin is taken low the HS FET drive is not affected but
diode emulation mode is activated for the LS FET. See
Table 2 for a comprehensive view of all logic inputs and
corresponding drive conditions.
Table 2. Control Logic Truth Table
DISB#
L
H
H
H
H
H
SMOD
X
L
L
X
H
H
PWM
X
H
L
Tri State
H
L
GH
L
H
L
L
H
L
GL
L
L
See Note
L
L
H
Note: Diode emulation mode is activated when SMOD pin is held low.
Gate Drives
AOZ5066QI has an internal high current high speed
driver that generates the floating gate drive for the
HS FET and a complementary drive for the LS FET.
Propagation delays between transitions of the PWM
waveform and corresponding gate drives are kept to the
minimum. An internal shoot through protection scheme
ensures that neither MOSFET turns on while the other
one is still conducting, thereby preventing shoot through
condition of the input current. When the PWM signal
makes a transition from H L or L H, the
corresponding gate drive GH or GL begins to turn off.
The adaptive timing circuit monitors the falling edge of
the gate voltage and when the level goes below 1V, the
complementary gate driver is turned on. The dead time
between the two switches is minimized, at the same time
preventing cross conduction across the input bus. The
adaptive circuit also monitors the switching node VSWH
and ensures that transition from one MOSFET to another
always takes place without cross conduction, even under
transient and abnormal conditions of operation.
The gate pins GH and GL are brought out on pins 6 and
36 respectively. However these connections are not
made directly to MOSFET gate pads and their voltage
measurement may not reflect the actual gate voltage
applied inside the package. The gate connections are
primarily for functional tests during manufacturing and no
connections should be made to them in the application.
Thermal Shutdown
The module temperature is internally sensed and an
alarm is asserted if it exceeds 150°C. The alarm is reset
when the temperature cools down to 135°C. The THDN
is an open drain pin that is pulled to CGND to indicate an
overtemperature condition. It may be pulled up to VCIN
through a resistor for monitoring purposes.
PCB Layout Guidelines
AOZ5066 is a high current module rated for operation up
to 1MHz. This requires extremely fast switching speeds
to keep the switching losses and device temperatures
within limits. Having a robust gate driver integrated in the
package helps to minimise the driver-to-MOSFET gate
pad connections without involving the parasitics of the
package or PCB traces. While excellent switching
speeds are achieved, correspondingly high levels of dv/dt
and di/dt will be observed throughout the power train
which requires careful attention to PCB layout to
minimise voltage spikes and other transients. As with any
synchronous buck converter layout the critical
requirement is to minimise the area of the primary
switching current loop, formed by the VIN, VSWH and
the input bypass capacitor Cin. The PCB design is
somewhat simplified because of the optimized pin out in
AOZ5066QI. The bulk of VIN and PGND pins are located
adjacent to each other and the input bypass capacitors
should be placed as close as possible to these pins. The
area of the secondary switching loop, formed by VSWH,
output inductor and output capacitor Cout is the next
critical parameter. The ground plane should be extended
and the negative pins of Cout should be returned to it,
again as close as possible to the device pins.
While AOZ5066QI is extremely efficient it can still
dissipate up to 6W of heat which requires attention to
thermal design. MOSFETs in the package are directly
attached to individual exposed pads to simplify thermal
management. Both VIN and VSWH pads should be
attached to large areas of PCB copper. Thermal reliefs
should be avoided to ensure proper heat dissipation to
the board. An inner power plane layer dedicated to VIN,
typically the 12V system input, is desirable and vias
should be provided near the device to connect the VIN
Rev. 3.0 December 2013
www.aosmd.com
Page 11 of 16
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet AOZ5066.PDF ] | |
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