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PDF AOZ5049QI Data sheet ( Hoja de datos )
| Número de pieza | AOZ5049QI | |
| Descripción | DrMOS Power Module | |
| Fabricantes | Alpha & Omega Semiconductors | |
| Logotipo |  |
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AOZ5049QI
High-Current, High-Performance
DrMOS Power Module
General Description
The AOZ5049QI is a high efficiency synchronous buck
power stage module consisting of two asymmetrical
MOSFETs and an integrated driver. The MOSFETs are
individually optimized for operation in the synchronous
buck configuration. The High Side (HS) MOSFET is
optimized to achieve low capacitance and gate charge
for fast switching with low duty cycle operation. The Low
Side (LS) MOSFET has ultra low on-resistance to
minimize conduction loss. The compact 3.5mm x 5mm
QFN package is optimally chosen and designed to
minimize parasitic inductance for minimal EMI signature.
The AOZ5049QI is intended for use with TTL and tri-state
compatibility by using both the PWM and /or FCCM inputs
for accurate control of the power MOSFETs.
A number of features provided make the AOZ5049QI a
highly versatile power module. The bootstrap supply
diode is integrated in the driver. The LS MOSFET can be
driven into diode emulation mode to provide
asynchronous operation when required. The pinout is
optimized for low inductance routing of the converter,
keeping the parasitics and their effects to a minimum.
Features
4.5V to 25V power supply range
4.5V to 5.5V driver supply range
Up to 35A output current
Integrated bootstrap Schottky diode
Up to 2MHz switching operation
Tri-state FCCM/PWM input compatible
Under-voltage lockout protection
Single pin control for shutdown/diode emulation/CCM
operation
Small 3.5mm x 5mm QFN-24L package
Applications
Servers
Notebook computers
VRMs for motherboards
Point-of-load DC/DC converters
Memory and graphic cards
Video gaming consoles
Typical Application Circuit
AOZ5049QI
VIN
FCCM
PWM
Drive Logic
and
Delay
PGND
PGND
+5
Cvcc
VCC
4.5V to 25V
BOOT
Cvin
Cboot
VSWH
L
VOUT
PGND
Cout
PGND
Rev. 3.0 June 2016
www.aosmd.com
Page 1 of 14
1 page  
AOZ5049QI
Electrical Characteristics(4)
TA = 25°C, VIN = 12V, VCC = 5V unless otherwise specified.
Symbol
Parameter
VIN
VCC
RJC
RJA
Power Stage Power Supply
Driver Power Supply
Thermal Resistance
INPUT SUPPLY AND UVLO
VCC
VCC_HYST
Under-Voltage Lockout
IVCC_SD Shutdown Bias Supply Current
Control Circuit Bias Current
IVCC
Switching Current (IBIAS +
IDRV)
PWM INPUT
VPWMH
VPWML
PWM Input High Threshold
PWM Input Low Threshold
IPWM
PWM Pin Input Current
VTRI
PWM Input Tri-State
Threshold Window
FCCM INPUT
VFCCMH
VFCCML
FCCM Enable Threshold
IFCCM
FCCM Pin Input Current
VTRI
FCCM Input Tri-State
Threshold Window
VTRI_HYST
FCCM Input Threshold
Hysteresis
tPTS PS4 Exit Latency
GATE DRIVER TIMING
tPDLU
tPDLL
tPDHU
PWM Falling to GH Turn-Off
PWM Raising to GL Turn-Off
GL Falling to GH Rising
Deadtime
tPDHL
GH/VSWH Falling to GL Rising
Deadtime
tTSSHD
tPTS
tLGMIN
Tri-State Shutdown Delay
Tri-State Propagation Delay
Low-Side Minimum On-Time
Conditions
VCC = 5V
PCB Temp = 100°C
AOS Demo Board
VCC Rising
VCC Falling
FCCM = Floating (Shutdown)
VPWM = Internally Pulled Low
FCCM = 5V (CCM), VPWM = Floating
FCCM = 0V (DCM), VPWM = Floating
FCCM = 5V, VPWM = 800kHz
FCCM = 5V, VPWM = 1MHz
FCCM = 5V, VPWM = 1.5MHz
VPWM Rising, VCC = 5V
VPWM Falling, VCC = 5V
Source, PWM = 5V
Sink, PWM = 0V
PWM = High Impedance
FCCM Rising, VCC = 5V
Shutdown CCM
FCCM Falling, VCC = 5V
Shutdown DCM
Source, FCCM = 5V
Sink, FCCM = 0V
FCCM = High Impedance
Shutdown CCM Shutdown
DCM Shutdown DCM
VCC = 5V
PWM 10%, GH 90%
PWM 90%, GL 90%
GL 10%, GH 10%
VSWH @ 1V, GL 10%
TS to GH Falling, TS to GL Falling
TS Exit
FCCM = 0V
Notes:
4. All voltages are specified with respect to the corresponding PGND pin
5. Characterisation value. Not tested in production.
Rev. 3.0 June 2016
www.aosmd.com
Min.
4.5
4.5
Typ.
3
10
Max.
25
5.5
Units
V
V
°C / W
°C / W
3.4 3.9
500
3
80
120
27
34
48
V
mV
A
A
A
mA
mA
mA
4.1
0.7
+250
-250
1.1 3.9
V
V
A
A
V
3.8
1.2
+50
-50
1.4 3.4
300
15
18
25
20
20
175
35
350
V
V
A
A
V
mV
s
ns
ns
ns
ns
ns
ns
ns
Page 5 of 14
5 Page 
AOZ5049QI
VSWH
Figure 12. Bottom Layer PCB Layout (VSWH Copper Plane
Voided on Descending Layers)
Adding Vias Through Exposed Pads
Landing Pattern
The AOZ5049QI can be operated at a switching
frequency of up to 2MHz. This implies that the inherent
capacitive parameters of the HS and LS MOSFETs need
to be charged and discharge on each and every cycle.
Due to the back and forth conduction of these AC
currents flowing in and out of the input capacitors, the
exposed pads (VIN and PGND) would tend to heat up,
hence requiring thermal venting. Positioning vias through
the landing pattern of the VIN and PGND thermal pads
will help quickly facilitate the thermal build up and spread
the heat much more quickly towards the surrounding
copper layers descending from the top layer.
The exposed pads dimensional footprint of the 3.5x5
QFN package is shown on Figure 13. For optimal thermal
relief, it is recommended to fill the PGND and VIN
exposed landing pattern with 10mil diameter vias. 10mil
via diameter is a commonly used as it is optimally cost
effective based on the tooling bit used in manufacturing.
Each via is associated with a 20mil diameter keep out.
Maintain a 5mil clearance (127µm) around the inside
edge of each exposed pad in an event of solder overflow,
potentially shorting with the adjacent expose thermal
pad.
1
PWM
PGND
Area Clearance from
Edge of Thermal Pads
FCCM
VSWH
3500µm
BOOT
2960µm GH
VSWH
VIA
1530µm
5000µm
1874µm
2181µm
508µm (20mil)
Diameter Kept
Out
254µm (10mil)
Diameter Drill bit
for VIA hole
127µm (5mil)
Clearance from
exposed pad
edge
Figure 13. Exposed Pad Land Pattern and Recommended Via Placements
Rev. 3.0 June 2016
www.aosmd.com
Page 11 of 14
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet AOZ5049QI.PDF ] | |
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