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853S011B 데이터시트 PDF




IDT에서 제조한 전자 부품 853S011B은 전자 산업 및 응용 분야에서
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부품번호 853S011B 기능
기능 LVPECL/ ECL Fanout Buffer
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853S011B 데이터시트, 핀배열, 회로
Low Skew, 1-to-2, Differential-to-2.5V, 3.3V
LVPECL/ ECL Fanout Buffer
853S011B
Datasheet
General Description
The 853S011B is a low skew, high performance 1-to-2
Differential-to-2.5V/3.3V LVPECL/ECL Fanout Buffer. The
853S011B is characterized to operate from either a 2.5V or a 3.3V
power supply. Guaranteed output and part-to-part skew
characteristics make the 853S011B ideal for those clock distribution
applications demanding well defined performance and repeatability.
Features
Two differential 2.5V, 3.3V LVPECL/ECL outputs
One differential PCLK, nPCLK input pair
PCLK, nPCLK pairs can accept the following
differential input levels: LVPECL, LVDS, CML, SSTL
Maximum output frequency: >2.5GHz
Translates any single-ended input signal to 3.3V LVPECL levels
with resistor bias on nPCLK input
Output skew: 5ps (typical)
Part-to-part skew: 130ps (maximum)
Propagation delay: 355ps (maximum)
LVPECL mode operating voltage supply range:
VCC = 2.375V to 3.8V, VEE = 0V
ECL mode operating voltage supply range:
VCC = 0V, VEE = -3.8V to -2.375V
-40°C to 85°C ambient operating temperature
Available lead-free (RoHS 6) package
Block Diagram
PCLK Pulldown
nPCLK Pullup/Pulldown
Q0
nQ0
Q1
nQ1
©2016 Integrated Device Technology, Inc.
Pin Assignment
Q0 1
nQ0 2
Q1 3
nQ1 4
8 VCC
7 PCLK
6 nPCLK
5 VEE
853S011B
8-Lead SOIC, 150MIL
3.90mm x 4.90mm x 1.37mm package body
M Package
Top View
8-Lead TSSOP, 118MIL
3.0mm x 3.0mm x 0.97mm package body
G Package
Top View
1 Revision B, February 23, 2016




853S011B pdf, 반도체, 판매, 대치품
853S011B Datasheet
Table 3B. LVPECL DC Characteristics, VCC = 3.3V; VEE = 0V, TA = -40°C to 85°C
-40°C
25°C
Symbol Parameter
Min Typ Max Min Typ Max
VOH
VOL
VPP
VCMR
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Input Voltage
Input High Voltage Common
Mode Range; NOTE 2
2.245
1.380
150
2.350
1.520
800
2.450
1.660
1200
2.265
1.415
150
2.340
1.510
800
2.415
1.605
1200
1.2 3.3 1.2
3.3
IIH
Input
High Current
PCLK, nPCLK
200
200
IIL
Input
PCLK
Low Current nPCLK
-10
-200
-10
-200
Min
2.245
1.405
150
1.2
-10
-200
85°C
Typ
2.320
1.500
800
Max
2.395
1.595
1200
3.3
200
Units
V
V
mV
V
µA
µA
µA
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE: Input and output parameters vary 1:1 with VCC. VEE can vary +0.925V to -0.5V.
NOTE 1: Outputs terminated with 50to VCCO – 2V.
NOTE 2: Common mode voltage is defined as VIH.
Table 3C. LVPECL DC Characteristics, VCC = 2.5V; VEE = 0V, TA = -40°C to 85°C
-40°C
25°C
Symbol Parameter
Min Typ Max Min Typ Max
VOH
VOL
VPP
VCMR
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Input Voltage
Input High Voltage Common
Mode Range; NOTE 2
1.445
0.580
150
1.550
0.720
800
1.650
0.860
1200
1.2 2.5
1.405
0.615
150
1.2
1.540
0.710
800
1.615
0.805
1200
2.5
IIH
Input
High Current
PCLK, nPCLK
200
200
IIL
Input
PCLK
Low Current nPCLK
-10
-200
-10
-200
Min
1.445
0.605
150
1.2
-10
-200
85°C
Typ
1.520
0.700
800
Max
1.595
0.795
1200
2.5
200
Units
V
V
mV
V
µA
µA
µA
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE: Input and output parameters vary 1:1 with VCC. VEE can vary +0.925V to -0.5V.
NOTE 1: Outputs terminated with 50to VCCO – 2V.
NOTE 2: Common mode voltage is defined as VIH.
©2016 Integrated Device Technology, Inc.
4
Revision B, February 23, 2016

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853S011B 전자부품, 판매, 대치품
853S011B Datasheet
Additive Phase Jitter
The spectral purity in a band at a specific offset from the fundamental
compared to the power of the fundamental is called the dBc Phase
Noise. This value is normally expressed using a Phase noise plot
and is most often the specified plot in many applications. Phase noise
is defined as the ratio of the noise power present in a 1Hz band at a
specified offset from the fundamental frequency to the power value of
the fundamental. This ratio is expressed in decibels (dBm) or a ratio
of the power in the 1Hz band to the power in the fundamental. When
the required offset is specified, the phase noise is called a dBc value,
which simply means dBm at a specified offset from the fundamental.
By investigating jitter in the frequency domain, we get a better
understanding of its effects on the desired application over the entire
time record of the signal. It is mathematically possible to calculate an
expected bit error rate given a phase noise plot.
Additive Phase Jitter @ 155.52MHz
12kHz to 20MHz = 0.026ps (typical)
Offset from Carrier Frequency (Hz)
As with most timing specifications, phase noise measurements has
issues relating to the limitations of the equipment. Often the noise
floor of the equipment is higher than the noise floor of the device. This
is illustrated above. The device meets the noise floor of what is
shown, but can actually be lower. The phase noise is dependent on
the input source and measurement equipment.
©2016 Integrated Device Technology, Inc.
7
Revision B, February 23, 2016

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853S011B

LVPECL/ ECL Fanout Buffer

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