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854S057B 데이터시트 PDF




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부품번호 854S057B 기능
기능 4:1 or 2:1 LVDS Clock Multiplexer
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854S057B 데이터시트, 핀배열, 회로
4:1 or 2:1 LVDS Clock Multiplexer with
Internal Input Termination
854S057B
Datasheet
General Description
The 854S057B is a 4:1 or 2:1 LVDS Clock Multiplexer which can
operate up to 2GHz. The PCLK, nPCLK pairs can accept most
standard differential input levels. Internal termination is provided on
each differential input pair. The 854S057B operates using a 2.5V
supply voltage. The fully differential architecture and low propagation
delay make it ideal for use in high speed multiplexing applications.
The select pins have internal pulldown resistors. Leaving one input
unconnected (pulled to logic low by the internal resistor) will
transform the device into a 2:1 multiplexer. The SEL1 pin is the most
significant bit and the binary number applied to the select pins will
select the same numbered data input (i.e., 00 selects PCLK0,
nPCLK0).
Features
High speed differential multiplexer. The device can be configured
as either a 4:1 or 2:1 multiplexer
One LVDS output pair
Four selectable PCLK, nPCLK inputs with internal termination
PCLKx, nPCLKx pairs can accept the following differential
input levels: LVPECL, LVDS, CML, SSTL
Maximum output frequency: >2GHz
Part-to-part skew: 200ps (maximum)
Propagation delay: 800ps (maximum)
Additive phase jitter, RMS: 0.065ps (typical)
Full 2.5V power supply
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package
Block Diagram
VT0
50
PCLK0
nPCLK0
VT1
50
50
PCLK1
nPCLK1
50
VT2
50
PCLK2
nPCLK2
VT3
50
50 50
PCLK3
nPCLK3
SEL1 Pulldown
SEL0 Pulldown
00
01
10
11
Q
nQ
©2016 Integrated Device Technology, Inc.
Pin Assignment
VDD
PCLK0
VT0
nPCLK0
SEL1
SEL0
PCLK1
VT1
nPCLK1
GND
1
2
3
4
5
6
7
8
9
10
20 VDD
19 PCLK3
18 VT3
17 nPCLK3
16 Q
15 nQ
14 PCLK2
13 VT2
12 nPCLK2
11 GND
854S057B
20-Lead TSSOP
4.4mm x 6.5mm x 0.925mm package body
G Package
Top View
1 Revision B, February 10, 2016




854S057B pdf, 반도체, 판매, 대치품
854S057B Datasheet
Table 4D. LVDS DC Characteristics, VDD = 2.5V ± 5%, TA = -40°C to 85°C
Symbol Parameter
Test Conditions
VOD
VOD
VOS
VOS
Differential Output Voltage
VOD Magnitude Change
Offset Voltage
VOS Magnitude Change
Minimum
225
1.125
Typical
325
4
1.25
5
Maximum
425
35
1.375
25
Units
mV
mV
V
mV
Table 5. AC Characteristics, VDD = 2.5V ± 5%, TA = -40°C to 85°C
Symbol
Parameter
Test Conditions
Minimum Typical Maximum Units
fMAX
tPD
tsk(pp)
Output Frequency
Propagation Delay; NOTE 1
Part-to-Part Skew; NOTE 2, 3
>2 GHz
300 800 ps
200 ps
tsk(i)
Input Skew
40 ps
tjit
Buffer Additive Phase Jitter, RMS;
622.08MHz, Integration Range:
refer to Additive Phase Jitter Section
12kHz – 20MHz
0.065
ps
tR / tF
Output Rise/Fall Time
20% to 80%
700MHz
50
49
250 ps
51 %
odc Output Duty Cycle
ƒ1.1GHz
47
53 %
ƒ2GHz
43
57 %
MUXISOLATION MUX Isolation
ƒ= 500MHz
-65 dBm
NOTE: All parameters measured at ƒ1.9GHz unless noted otherwise.
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal equilibrium
has been reached under these conditions.
NOTE 1: Measured from the differential input crossing point to the differential output crossing point.
NOTE 2: Defined as skew between different devices operating at the same supply voltage, same frequency and with equal load conditions.
Using the same type of inputs on each device, the output is measured at the differential cross point.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
©2016 Integrated Device Technology, Inc.
4
Revision B, February 10, 2016

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854S057B 전자부품, 판매, 대치품
Parameter Measurement Information, continued
nQ
20%
Q
80%
tR
80%
tF
VOD
20%
nQ
Q
854S057B Datasheet
Output Rise/Fall Time
Output Duty Cycle/Pulse Width/Period
Differential Output Voltage Setup
Offset Voltage Setup
©2016 Integrated Device Technology, Inc.
7
Revision B, February 10, 2016

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854S057B

4:1 or 2:1 LVDS Clock Multiplexer

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