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9DMV0431 데이터시트 PDF




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부품번호 9DMV0431 기능
기능 2:4 1.8V PCIe Gen1-2-3 Clock Mux
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9DMV0431 데이터시트, 핀배열, 회로
2:4 1.8V PCIe Gen1-2-3 Clock Mux
9DMV0431
DATASHEET
General Description
The 9DMV0431 is a member of IDT's SOC-Friendly 1.8V
Very-Low-Power (VLP) PCIe Gen1-2-3 family. Each of the 4
outputs has its own dedicated OE# pin for optimal system
control and power management. The part provides
asynchronous and glitch-free switching modes.
Recommended Application
2:4 PCIe Gen1-2-3 clock multiplexer
Output Features
4 -Low-Power (LP) HCSL DIF pairs
Key Specifications
DIF additive cycle-to-cycle jitter <5ps
DIF phase jitter is PCIe Gen1-2-3 compliant
Additive phase jitter @ 125MHz: 420fs rms typical (12kHz
to 20MHz)
DIF output-to-output skew <50ps
Features/Benefits
LP-HCSL outputs; save 8 resistors compared to standard
HCSL outputs
1.8V operation; 36mW typical power consumption
Selectable asynchronous or glitch-free switching; allows
the mux to be selected at power up even if both inputs are
not running, then transition to glitch-free switching mode
Spread Spectrum Compatible; supports EMI reduction
OE# pins; support DIF power management
HCSL differential inputs; can be driven by common clock
sources
1MHz to 200MHz operating frequency
Space saving 24-pin 4x4mm VFQFPN; minimal board
space
Block Diagram
^OE(3:0)#
DIF_INA
DIF_INB
vSW_MODE
^SEL_A_B#
4
,
A
B
DIF3
DIF2
DIF1
DIF0
9DMV0431 REVISION B 01/26/15
1
©2015 Integrated Device Technology, Inc.




9DMV0431 pdf, 반도체, 판매, 대치품
9DMV0431 DATASHEET
Test Loads
Low-Power HCSL Output Test Load
Rs
Low-Power HCSL
Output
Rs
Alternate Differential Output Terminations
Rs Zo Units
33 100 Ohms
27 85
Driving LVDS
Driving LVDS
Rs
Device
Rs
Cc
Cc
Zo=100ohms
5 inches
2pF 2pF
3.3V
R7a
L4
R8a
R7b
R8b
LVDS Clock
input
Driving LVDS inputs
Value
Receiver has Receiver does not
Component
termination have termination Note
R7a, R7b
10K ohm
140 ohm
R8a, R8b
5.6K ohm
75 ohm
Cc
0.1 uF
0.1 uF
Vcm
1.2 volts
1.2 volts
2:4 1.8V PCIE GEN1-2-3 CLOCK MUX
4
REVISION B 01/26/15

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9DMV0431 전자부품, 판매, 대치품
9DMV0431 DATASHEET
Electrical Characteristics–Output Duty Cycle, Jitter, Skew and PLL Characteristics
TA = TAMB, Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX
UNITS NOTES
Duty Cycle Distortion
tDCD Measured differentially, Bypass Mode @100MHz -1 -0.15 1
% 1,3
Skew, Input to Output
tpdBYP
Bypass Mode, VT = 50%
1819 2365 3075
ps
1
Skew, Output to Output
tsk3
VT = 50%
16 50 ps 1,4
Jitter, Cycle to cycle tjcyc-cyc
Additive Jitter in Bypass Mode
0.1 5
ps 1,2
1 Guaranteed by design and characterization, not 100% tested in production.
2 Measured from differential waveform
3 Duty cycle distortion is the difference in duty cycle between the output and the input clock when the device is operated in bypass mode
4 All outputs at default slew rate
5 The MIN/TYP/MAX values of each BW setting track each other, i.e., Low BW MAX will never occur with Hi BW MIN.
Electrical Characteristics–Phase Jitter Parameters
TA = TAMB, Supply Voltages per normal operation conditions, See Test Loads for Loading Conditions
PARAMETER
Additive Phase Jitter,
Bypass Mode
SYMBOL
tjphPCIeG1
tjphPCIeG2
tjphPCIeG3
CONDITIONS
PCIe Gen 1
PCIe Gen 2 Lo Band
10kHz < f < 1.5MHz
PCIe Gen 2 High Band
1.5MHz < f < Nyquist (50MHz)
PCIe Gen 3
(PLL BW of 2-4 or 2-5MHz, CDR = 10MHz)
MIN TYP
1.3
0.1
0.1
0.065
MAX
5
0.3
0.2
0.1
INDUSTRY
LIMIT UNITS Notes
N/A ps (p-p) 1,2,3,5
N/A ps 1,2,3,4,
(rms)
5
N/A ps 1,2,3,4
(rms)
N/A ps 1,2,3,4
(rms)
125MHz, 1.5MHz to 10MHz, -20dB/decade
tjph125M0 rollover < 1.5MHz, -40db/decade rolloff > 10MHz
fs
285 300 N/A (rms) 1,6
125MHz, 12KHz to 20MHz, -20dB/decade
tjph125M1 rollover < 12kHz, -40db/decade rolloff > 20MHz
420 450
N/A
fs
(rms)
1Guaranteed by design and characterization, not 100% tested in production.
2 See http://www.pcisig.com for complete specs
3 Sample size of at least 100K cycles. This figures extrapolates to 108ps pk-pk @ 1M cycles for a BER of 1-12.
4 For RMS figures, additive jitter is calculated by solving the following equation: Additive jitter = SQRT[(total jitter)^2 - (input jitter)^2]
5 Driven by 9FGU0831 or equivalent
6 Rohde&Schartz SMA100
1,6
REVISION B 01/26/15
7 2:4 1.8V PCIE GEN1-2-3 CLOCK MUX

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9DMV0431

2:4 1.8V PCIe Gen1-2-3 Clock Mux

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