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9ZML1232 데이터시트 PDF




IDT에서 제조한 전자 부품 9ZML1232은 전자 산업 및 응용 분야에서
광범위하게 사용되는 반도체 소자입니다.


 

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부품번호 9ZML1232 기능
기능 2:12 LOW POWER DIFFERENTIAL Z-BUFFER MUX
제조업체 IDT
로고 IDT 로고


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9ZML1232 데이터시트, 핀배열, 회로
2:12 LOW POWER DIFFERENTIAL Z-BUFFER MUX FOR PCIE AND QPI/UPI
DATASHEET
9ZML1232
General Description
The 9ZML1232 is a 2-input/12-output differential mux for
use in servers. It meets the demanding DB1200ZL
performance specifications and utilizes Low-Power
HCSL-compatible outputs to reduce power consumption
and termination components. It is suitable for PCI-Express
Gen1/2/3 or QPI/UPI applications, and uses a fixed external
feedback to maintain low drift for demanding QPI
applications.
Recommended Application
Clock Mux for Romley, Grantley and Purley Servers
Output Features
12 - Low-Power (LP) HCSL Output Pairs
Block Diagram
y
Features/Benefits
Fixed feedback path; 0ps input-to-output delay
9 Selectable SMBus addresses; multiple devices can
share same SMBus segment
Separate VDDIO for outputs; allows maximum power
savings
PLL or bypass mode; PLL can dejitter incoming clock
Hardware or Software-selectable PLL BW; minimizes
jitter peaking in downstream PLL's
Spread spectrum compatible; tracks spreading input
clock for EMI reduction
SMBus Interface; unused outputs can be disabled
Differential outputs are Low/Low in power down;
maximum power savings
Key Specifications
Cycle-to-cycle jitter <50ps
Output-to-output skew <65 ps
Input-to-output delay: Fixed at 0 ps
Input-to-output delay variation <50ps
Phase jitter: PCIe Gen3 <1ps rms
Phase jitter: QPI/UPI 9.6GB/s <0.2ps rms
y
OE(11:0)#
DIF_INB
DIF_INB#
DIF_INA
DIF_INA#
HIBW_BYPM_LOBW#
SEL_A_B#
CKPWRGD/PD#
SMB_A0_tri
SMB_A1_tri
SMBDAT
SMBCLK
Logic
Z-PLL
(SS Compatible)
FBOUT_NC
DIF(11:0)
IDT® 2:12 LOW POWER DIFFERENTIAL Z-BUFFER MUX FOR PCIE AND QPI/UPI
1 9ZML1232
REV E 112015




9ZML1232 pdf, 반도체, 판매, 대치품
9ZML1232
2:12 LOW POWER DIFFERENTIAL Z-BUFFER MUX FOR PCIE AND QPI/UPI
Pin Descriptions (cont.)
PIN #
PIN NAME
PIN TYPE
DESCRIPTION
35 ^OE2#
IN
Active low input for enabling DIF pair 2. This pin has an internal pull-up resistor.
1 =disable outputs, 0 = enable outputs
36 ^OE3#
IN
Active low input for enabling DIF pair 3. This pin has an internal pull-up resistor.
1 =disable outputs, 0 = enable outputs
37 ^OE4#
IN
Active low input for enabling DIF pair 4. This pin has an internal pull-up resistor.
1 =disable outputs, 0 = enable outputs
38 ^OE5#
39 GND
40 VDDIO
41 DIF_4
42 DIF_4#
43 DIF_5
44 DIF_5#
45 VDD
46 GND
47 DIF_6
48 DIF_6#
49 DIF_7
50 DIF_7#
51 GND
52 VDDIO
53 ^OE6#
54 ^OE7#
55 ^OE8#
56 ^OE9#
57 VDDIO
58 GND
59 DIF_8
60 DIF_8#
61 DIF_9
62 DIF_9#
63 GND
64 VDD
65 DIF_10
66 DIF_10#
67 DIF_11
68 DIF_11#
69 VDDIO
70 GND
71 ^OE10#
72 ^OE11#
IN
PWR
PWR
OUT
OUT
OUT
OUT
PWR
PWR
OUT
OUT
OUT
OUT
PWR
PWR
IN
IN
IN
IN
PWR
PWR
OUT
OUT
OUT
OUT
PWR
PWR
OUT
OUT
OUT
OUT
PWR
PWR
IN
IN
Active low input for enabling DIF pair 5. This pin has an internal pull-up resistor.
1 =disable outputs, 0 = enable outputs
Ground pin.
Power supply for differential outputs
0.7V differential true clock output
0.7V differential Complementary clock output
0.7V differential true clock output
0.7V differential Complementary clock output
Power supply, nominal 3.3V
Ground pin.
0.7V differential true clock output
0.7V differential Complementary clock output
0.7V differential true clock output
0.7V differential Complementary clock output
Ground pin.
Power supply for differential outputs
Active low input for enabling DIF pair 6. This pin has an internal pull-up resistor.
1 =disable outputs, 0 = enable outputs
Active low input for enabling DIF pair 7. This pin has an internal pull-up resistor.
1 =disable outputs, 0 = enable outputs
Active low input for enabling DIF pair 8. This pin has an internal pull-up resistor.
1 =disable outputs, 0 = enable outputs
Active low input for enabling DIF pair 9. This pin has an internal pull-up resistor.
1 =disable outputs, 0 = enable outputs
Power supply for differential outputs
Ground pin.
0.7V differential true clock output
0.7V differential Complementary clock output
0.7V differential true clock output
0.7V differential Complementary clock output
Ground pin.
Power supply, nominal 3.3V
0.7V differential true clock output
0.7V differential Complementary clock output
0.7V differential true clock output
0.7V differential Complementary clock output
Power supply for differential outputs
Ground pin.
Active low input for enabling DIF pair 10. This pin has an internal pull-up resistor.
1 =disable outputs, 0 = enable outputs
Active low input for enabling DIF pair 11. This pin has an internal pull-up resistor.
1 =disable outputs, 0 = enable outputs
IDT® 2:12 LOW POWER DIFFERENTIAL Z-BUFFER MUX FOR PCIE AND QPI/UPI
4 9ZML1232
REV E 112015

4페이지










9ZML1232 전자부품, 판매, 대치품
9ZML1232
2:12 LOW POWER DIFFERENTIAL Z-BUFFER MUX FOR PCIE AND QPI/UPI
Electrical Characteristics–DIF 0.7V Low Power Differential Outputs
TA = TCOM; Supply Voltage VDD/VDDA = 3.3 V +/-5%, VDDIO = 1.05 to 3.3V +/-5%. See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS NOTES
Slew rate
Trf
Scope averaging on
1 3.3 4 V/ns 1, 2, 3
Slew rate matching Trf Slew rate matching, Scope averaging on
2 20 % 1, 2, 4
Voltage High
Voltage Low
VHigh
VLow
Statistical measurement on single-ended signal 660 804 850
using oscilloscope math function. (Scope
mV
averaging on)
-150 19 150
1
1
Max Voltage
Min Voltage
Vmax
Vmin
Measurement on single ended signal using
absolute value. (Scope averaging off)
885 1150 mV
-300 -29
1
1
Vswing
Vswing
Scope averaging off
300 1569
mV 1, 2
Crossing Voltage (abs)
Crossing Voltage (var)
Vcross_abs
-Vcross
Scope averaging off
Scope averaging off
300 465 550 mV 1, 5
12 140 mV 1, 6
1Guaranteed by design and characterization, not 100% tested in production. CL = 2pF with RS = 27for Zo = 85differential trace
impedance).
2 Measured from differential waveform
3 Slew rate is measured through the Vswing voltage range centered around differential 0V. This results in a +/-150mV window around
differential 0V.
4 Matching applies to rising edge rate for Clock and falling edge rate for Clock#. It is measured using a +/-75mV window centered on
the average cross point where Clock rising meets Clock# falling. The median cross point is used to calculate the voltage thresholds the
oscilloscope is to use for the edge rate calculations.
5 Vcross is defined as voltage where Clock = Clock# measured on a component test board and only applies to the differential rising
edge (i.e. Clock rising and Clock# falling).
6 The total variation of all Vcross measurements in any particular system. Note that this is a subset of Vcross_min/max (Vcross
absolute) allowed. The intent is to limit Vcross induced modulation by setting -Vcross to be smaller than Vcross absolute.
Electrical Characteristics–Current Consumption
TA = TCOM; Supply Voltage VDD/VDDA = 3.3 V +/-5%, VDDIO = 1.05 to 3.3V +/-5%. See Test Loads for Loading Conditions
PARAMETER
SYMBOL
CONDITIONS
MIN TYP MAX UNITS
Operating Supply Current
IDDVDD
IDDVDDA/R
IDDVDDIO
All outputs @100MHz, CL = 2pF; Zo=85
All outputs @100MHz, CL = 2pF; Zo=85
All outputs @100MHz, CL = 2pF; Zo=85
13 35
14 20
86 100
mA
mA
mA
IDDVDDPD
All differential pairs low/low
0.7 4
mA
Powerdown Current
IDDVDDA/RPD
All differential pairs low/low
5 mA
IDDVDDIOPD
All differential pairs low/low
0.2 mA
1 Guaranteed by design and characterization, not 100% tested in production.
2 With input clock running. Stopping the input clock will result in lower numbers.
NOTES
1
1
1
1,2
1,2
1,2
IDT® 2:12 LOW POWER DIFFERENTIAL Z-BUFFER MUX FOR PCIE AND QPI/UPI
7 9ZML1232
REV E 112015

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9ZML1232

2:12 LOW POWER DIFFERENTIAL Z-BUFFER MUX

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