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9ZX21200 데이터시트 PDF




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부품번호 9ZX21200 기능
기능 12-OUTPUT DIFFERENTIAL Z-BUFFER
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9ZX21200 데이터시트, 핀배열, 회로
12-OUTPUT DIFFERENTIAL Z-BUFFER FOR PCIE GEN3 AND QPI
DATASHEET
9ZX21200
Description
The 9ZX21200 is a small-footprint 12-output differential
buffer that meets all the performance requirements of the
Intel DB1200Z specification. The 9ZX21200 is backwards
compatible to PCIe Gen1 and Gen2 applications. A fixed,
internal feedback path maintains low drift for critical QPI
applications. In bypass mode, the 9ZX21200 can provide
outputs up to 150MHz.
Recommended Application
12-output PCIe Gen3/ QPI differential buffer for Romley and
newer platforms
Key Specifications
Cycle-to-cycle jitter <50ps
Output-to-output skew < 65 ps
Input-to-output delay variation <50ps
PCIe Gen3 phase jitter < 1.0ps RMS
QPI 9.6GT/s 12UI phase jitter < 0.2ps RMS
Features/Benefits
Space-saving 56-pin package
Fixed feedback path for 0ps input-to-output delay
9 Selectable SMBus Addresses; Mulitple devices can
share the same SMBus Segment
4 OE# pins; Hardware control of four outputs
PLL or bypass mode; PLL can dejitter incoming clock
100MHz or 133MHz PLL mode operation; supports PCIe
and QPI applications
Selectable PLL bandwidth; minimizes jitter peaking in
downstream PLL's
Spread Spectrum Compatible; tracks spreading input
clock for low EMI
Software control of PLL Bandwidth and Bypass
Settings/PLL can dejitter incoming clock (B Rev only)
Output Features
12 - 0.7V differential HCSL output pairs
Block Diagram
OE(8,6,4,2)#
DIF_IN
DIF_IN#
Z-PLL
(SS Compatible)
DFB_OUT
DIF(11:0)
HIBW_BYPM_LOBW#
100M_133M#
CKPWRGD/PD#
SMB_A0_tri
SMB_A1_tri
SMBDAT
SMBCLK
Logic
IREF
IDT® 12-OUTPUT DIFFERENTIAL Z-BUFFER FOR PCIE GEN3 AND QPI
1
9ZX21200
REV D 041513




9ZX21200 pdf, 반도체, 판매, 대치품
9ZX21200
12-OUTPUT DIFFERENTIAL Z-BUFFER FOR PCIE GEN3 AND QPI
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the 9ZX21200. These ratings, which are standard
values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other
conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over
the recommended operating temperature range.
PARAMETER
SYM BO L
CONDITIONS
3.3V Core Supply Voltage VDD, VDDA
VD D for core logic and PLL
IO Supply Voltage
VDD
VDD for differential IO
Input Low Voltage
V IL
Input High Voltage
VIH
Except for SMBus interface
Input High Voltage
VIHSM B
SMBus clock and data pins
Storage Temperature
Ts
Junction Temperature
Input ESD protection
Tj
ESD prot
Human Body Model
1Guaranteed by design and characterization, not 100% tested in production.
2 Operation under these conditions is neither implied nor guaranteed.
MIN
GND-0. 5
-65
20 00
TYP
MAX
4.6
4.6
VD D+ 0.5V
5. 5V
1 50
1 25
UNITS
V
V
V
V
V
°C
°C
V
N OTE S
1,2
1,2
1
1
1
1
1
1
Electrical Characteristics–Clock Input Parameters
TA = TCOM; Supply Voltage VDD = 3.3 V +/-5%
PARAMETER
SYM BOL
CONDITIONS
Input High Voltage - DIF_IN
Input Low Voltage - DIF_IN
Input C ommon Mode Voltage
- DIF_IN
VIHD IF
VIL DIF
V CO M
Differential inputs
(single-ended measurement)
Differential inputs
(single-ended measurement)
Common Mode Input Voltage
Input Amplitude - DIF_IN
Input Slew Rate - DIF_IN
V S W ING
dv/dt
Peak to Peak value
Measured differentially
Input Leakage Current
Input Duty Cycle
IIN
dtin
VIN = VDD , VIN = GND
Measurement from differential wavefrom
Input Jitter - Cycle to Cycle
J DIF In
Differential Measurement
1 Guaranteed by design and characterization, not 100% tested in production.
2Slew rate measured through +/-75mV window centered around differential zero
MIN
60 0
VSS - 300
30 0
30 0
0.4
-5
45
0
TYP
80 0
0
MAX
1 150
3 00
1 000
1 450
8
5
55
1 25
UNITS NOTES
mV 1
mV 1
mV
mV
V/ns
uA
%
ps
1
1
1,2
1
1
1
IDT® 12-OUTPUT DIFFERENTIAL Z-BUFFER FOR PCIE GEN3 AND QPI
4
9ZX21200
REV D 041513

4페이지










9ZX21200 전자부품, 판매, 대치품
9ZX21200
12-OUTPUT DIFFERENTIAL Z-BUFFER FOR PCIE GEN3 AND QPI
Electrical Characteristics–Skew and Differential Jitter Parameters
TA = TCOM; Supply Voltage VDD = 3.3 V +/-5%
PARAMETER
SYMBOL
CONDITIONS
CLK_IN, DIF[x:0]
tSPO_PLL
Input-to-Output Skew in PLL mode
nominal value @ 25°C, 3.3V
CLK_IN, DIF[x:0]
tPD_BYP
Input-to-Output Skew in Bypass mode
nominal value @ 25°C, 3.3V
CLK_IN, DIF[x:0]
tDSPO_PLL
Input-to-Output Skew Varation in PLL mode
across voltage and temperature
MIN
-100
2.5
-50
TYP
29
3.7
MAX
100
4.5
50
UNITS NOTES
ps 1,2,4,5,8
ns 1,2,3,5,8
ps 1,2,3,5,8
CLK_IN, DIF[x:0]
Input-to-Output Skew Varation in Bypass mode
tDSPO_BYP
across voltage and temperature
-250
250 ps 1,2,3,5,8
CLK_IN, DIF[x:0]
tDTE
Random Differential Tracking error beween two
9ZX devices in Hi BW Mode
2.9
5
ps
(rms)
1,2,3,5,8
CLK_IN, DIF[x:0]
tDSSTE
Random Differential Spread Spectrum Tracking
error beween two 9ZX devices in Hi BW Mode
14 75 ps 1,2,3,5,8
DIF{x:0]
tSKEW_ALL
Output-to-Output Skew across all outputs
(Common to Bypass and PLL mode)
32 65 ps 1,2,3,8
PLL Jitter Peaking
PLL Jitter Peaking
PLL Bandwidth
PLL Bandwidth
Duty Cycle
Duty Cycle Distortion
Jitter, Cycle to cycle
jpeak-hibw
jpeak-lobw
pllHIBW
pllLOBW
tDC
tDCD
tjcyc-cyc
LOBW#_BYPASS_HIBW = 1
LOBW#_BYPASS_HIBW = 0
LOBW#_BYPASS_HIBW = 1
LOBW#_BYPASS_HIBW = 0
Measured differentially, PLL Mode
Measured differentially, Bypass Mode
@100MHz
PLL mode
Additive Jitter in Bypass Mode
0 1.8
0 0.7
2 3.1
0.7 1.1
45 49.6
-2 -0.2
15.7
0.1
2.5 dB 7,8
2 dB 7,8
4
MHz
8,9
1.4 MHz 8,9
55 % 1
2 % 1,10
50 ps 1,11
50 ps 1,11
Notes for preceding table:
1 Measured into fixed 2 pF load cap. Input to output skew is measured at the first output edge following the corresponding input.
2 Measured from differential cross-point to differential cross-point. This parameter can be tuned with external feedback path, if present.
3 All Bypass Mode Input-to-Output specs refer to the timing between an input edge and the specific output edge created by it.
4 This parameter is deterministic for a given device
5 Measured with scope averaging on to find mean value.
6. t is the period of the input clock
7 Measured as maximum pass band gain. At frequencies within the loop BW, highest point of magnification is called PLL jitter peaking.
8. Guaranteed by design and characterization, not 100% tested in production.
9 Measured at 3 db down or half power point.
10 Duty cycle distortion is the difference in duty cycle between the output and the input clock when the device is operated in bypass mode.
11 Measured from differential waveform
IDT® 12-OUTPUT DIFFERENTIAL Z-BUFFER FOR PCIE GEN3 AND QPI
7
9ZX21200
REV D 041513

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